98DX107-B0-LKJ1I000: Marvell Prestera L3 Switch Guide

The 0.15µm Switch Chip That Is Still Running Industrial Networks in 2025

A 0.15-micron CMOS process node from the early 2000s does not typically appear in new hardware designs two decades later. The dominant pressure in silicon is always toward smaller geometries, lower power, higher density, and more integrated features. By this logic, the Marvell Prestera DX107 should have disappeared from bills of materials years ago.

It has not, for a reason that has nothing to do with the performance of the silicon itself. The 98DX107 accumulated, over roughly fifteen years of production, a body of validated reference designs, a mature Linux kernel driver (the Marvell Prestera DSA driver in mainline Linux), an established evaluation board ecosystem (DB-DX107-10G, RD-DX107-48F4G), and a production track record in tens of thousands of deployed industrial switches, embedded gateways, and MikroTik CRS-series routers. That accumulated software and systems infrastructure is what keeps the 98DX107 in new designs — not because nothing newer exists, but because "newer" requires rebuilding the driver, revalidating the reference design, and requalifying the system software.

The 98DX107-B0-LKJ1I000 variant adds one more reason to remain on the BOM: it carries the I-Temp suffix, meaning it is qualified to operate from −40°C to +85°C junction temperature — the range required for industrial outdoor enclosures, ruggedized gateways, and telecommunications equipment exposed to seasonal temperature extremes. This combination of Layer 2/3 switching, 10 × SGMII interface flexibility, hardware L3 routing with 8K routing table entries, and validated industrial temperature operation in a 128-LQFP footprint remains useful in applications where validated field history matters more than the latest silicon generation.

1.0 What the 98DX107-B0-LKJ1I000 Is

Full designation: Marvell Prestera-DX107, industrial temperature, 128-LQFP package, silicon revision B0

Part number decode:

Field	Characters	Meaning
Marvell Prestera prefix	98	Identifies Prestera DX enterprise packet processor family
Product family	DX	Prestera DX series (enterprise/industrial switching)
Device identifier	107	DX107: 10-port GE L2/L3 packet processor
Silicon revision	-B0	Die revision B, stepping 0
Package code	-LKJ	128-pin LQFP, 14 mm × 20 mm body
Sub-variant	1	Variant code within LKJ package group
Temperature grade	I	Industrial: −40°C to +85°C junction
Distribution code	000	Standard commercial distribution

The companion commercial-temperature part is 98DX107-B0-LKJ1C000 ("C" = commercial, 0°C to +70°C). The LKJ suffix selects the 128-LQFP package; the alternate BGA variants use different package codes (BCW for HSBGA, 31 mm × 31 mm) and support the same electrical functionality with different PCB footprint requirements.

Marvell markets the 98DX107 under the Prestera-DX107 marketing name. Its full official description is "10-Port GE Multilayer L3-EDGE Switch" or in some product selector guides, "10-Port Gigabit Ethernet Packet Processor." The use of "Packet Processor" rather than "Switch" in Marvell's own literature is deliberate — the device includes not just a switch fabric but the programmable forwarding pipeline that enables hardware L3 routing, access control lists, and Quality of Service, which simple switch chips do not support.

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2.0 Specifications

From Marvell's Prestera DX product selector guide and published reference documentation:

Switching:

• Total ports: 10
• Port interfaces: 10 × SGMII (Serial Gigabit Media Independent Interface), each supporting 1000BASE-X (SFP), 100BASE-FX, and 10/100/1000BASE-T via external PHY
• Switch fabric capacity: Wire-speed non-blocking at 1 Gbps per port (20 Gbps aggregate)
• Switching layers: Layer 2 + Layer 3 (multilayer)

Tables:

• MAC address table: 4,096 entries (4K)
• IPv4 routing table: 8,192 entries (8K)
• ARP/neighbor table: 8K entries (shared with routing)

Quality of Service:

• 8 QoS groups, 8 ports per group
• 802.1p, DSCP, and port-based classification
• Weighted Round Robin (WRR) and Strict Priority scheduling

VLAN:

• IEEE 802.1Q tagged VLAN
• Port-based VLAN
• Q-in-Q (double VLAN tagging) support

Other features:

• IEEE 802.1D Spanning Tree Protocol (STP) / RSTP
• IEEE 802.3ad Link Aggregation (LACP)
• IGMP snooping
• Port mirroring
• Hardware-based ACL (Access Control Lists)
• MDC/MDIO management interface for external PHY control

Process and package:

• CMOS process: 0.15 µm
• Package (LKJ variant): 128-pin LQFP, 14 mm × 20 mm body
• Package (standard variant): 458-HSBGA, 31 mm × 31 mm body
• Industrial temperature (I suffix): −40°C to +85°C junction temperature
• Commercial temperature (C suffix): 0°C to +70°C junction temperature

Evaluation boards:

• DB-DX107-10G (standard evaluation board)
• RD-DX107-48F4G (reference design for 48-port FE + 4-port GE application using cascaded DX107 devices)

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3.0 Operating Modes and Layer 2/3 Capability

Layer 2 operation:

In L2 mode, the 98DX107 operates as a standard managed gigabit Ethernet switch with hardware-accelerated MAC learning, 802.1Q VLAN tagging, STP/RSTP, IGMP snooping, and port mirroring. Frames are forwarded based on destination MAC address lookup in the 4K-entry MAC table. This is the baseline operating mode and what most software stacks configure by default.

Layer 3 operation (hardware routing):

The "multilayer" designation distinguishes the 98DX107 from L2-only devices like the 98DX106. In L3 mode, the switch's forwarding pipeline performs IPv4 next-hop lookup using the 8K-entry routing table, decrements TTL, updates the destination MAC address to the next-hop router MAC, and forwards in hardware — entirely without software intervention on a per-packet basis. This is what MikroTik calls "L3 Hardware Offloading" in their RouterOS documentation for CRS-series switches based on Marvell Prestera chips.

The distinction between hardware-routed and software-routed traffic is substantial in embedded Linux router designs: software routing (the Linux kernel's IP forwarding) is limited by CPU throughput — a 500 MHz embedded MIPS core can forward perhaps 300–500 Mbps before saturating. Hardware L3 offloading in the 98DX107 routes at wire speed across all 10 ports regardless of CPU load.

98DX107 vs 98DX106 — the L3 versus L2+ distinction:

The 98DX106 (98DX106-B0-LKJ1I000) is Marvell's L2+ "SecureSmart" variant with a 256-entry MAC table and no L3 routing table. The 98DX107 adds hardware L3 with the 4K/8K tables described above. In the same 128-LQFP package and at nearly identical cost, the 98DX107 provides significantly higher capability. The choice between them historically came down to whether the application required only managed L2 switching (98DX106) or needed hardware-accelerated routing between VLANs and subnets (98DX107).

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4.0 SGMII Interfaces and External PHY Connectivity

All 10 ports of the 98DX107 are SGMII interfaces — they do not contain integrated PHY transceivers. Each port requires an external device to provide the physical layer to the network medium. This is fundamentally different from the 88E6020 Link Street switch, which had integrated PHYs. The implications for system design:

For copper (10/100/1000BASE-T): Connect each SGMII port to an external GE PHY such as the Marvell 88E1111, 88E1512, Realtek RTL8211, or Broadcom BCM54213. The SGMII serial interface carries 1 Gbps encoded data to/from the PHY; the PHY handles all analog front-end functions, auto-negotiation, and cable drive.

For fiber (1000BASE-X / 100BASE-FX): Connect each SGMII port directly to an SFP cage using SGMII-to-SFP direct connection (SFP modules with SGMII electrical interface), or via an SFP cage that directly terminates the SGMII signal from the switch. Many SFP modules present an SGMII electrical interface on their host-side connector, making the connection direct.

Mixed topologies: The 10 SGMII ports are individually configurable — some can connect to copper PHYs (for RJ-45 user ports) while others connect to SFP cages (for uplinks or fiber access), all within the same device. This flexibility made the DX107 popular for 8-port managed switches with 2 SFP uplinks, and for hybrid fiber/copper edge switches.

SGMII clock: Each SGMII interface requires a 125 MHz reference clock recovered from the serial stream (SGMII is self-clocked using 8b/10b encoding over a 1.25 Gbps differential serial link). No external clock per-port is required; the 98DX107's SGMII PLLs handle clock recovery.

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5.0 ⚠️ Four Pitfalls That Catch Designers Using This Part

Pitfall 1: Assuming the 98DX107 provides any user-facing Ethernet port directly

Every port on the 98DX107 is SGMII — there is no integrated PHY. A design that routes the 98DX107's SGMII outputs directly to RJ-45 connectors will not work. External GE PHY chips are required for every copper user port, adding BOM complexity, PCB area, and cost. Designs that specify the 98DX107 without accounting for 10 external PHY chips (or 10 SFP cages) in the system-level BOM are under-specified.

Pitfall 2: Confusing the 128-LQFP (LKJ) and 458-HSBGA package variants as interchangeable

The 98DX107 exists in two completely different packages: the 128-LQFP (LKJ suffix, 14 × 20 mm) and the 458-HSBGA (no LKJ in part number, 31 × 31 mm). These are not interchangeable — different pin counts, different pinout, completely different PCB footprints. The LQFP variant is smaller and easier to route on a standard 4–6 layer PCB; the HSBGA variant is a larger high-density BGA that requires more PCB layers and specialized via structures. Verify the package suffix before committing a PCB layout.

Pitfall 3: Expecting hardware L3 routing to work immediately without driver configuration

L3 hardware offloading in the 98DX107 is not automatic — it requires explicit configuration through the switch's management interface (MDC/MDIO or the higher-level software abstraction). In the Linux kernel's Prestera DSA driver, L3 offloading must be enabled and routing entries must be programmed into the hardware routing table. The Prestera driver's L3 support has evolved over multiple kernel versions; on kernel versions before approximately 5.15, full L3 hardware offloading may not be available or may require out-of-tree patches. Verify your target kernel version's Prestera driver L3 support status before committing to L3 hardware forwarding as a design requirement.

Pitfall 4: Using the I-Temp part (98DX107-B0-LKJ1I000) and then powering the system without adequate thermal management

The "I" suffix guarantees operation to −40°C to +85°C junction temperature, not ambient temperature. Junction temperature is the die temperature inside the LQFP package. In still air with a 128-LQFP package, the junction-to-ambient thermal resistance (θJA) is approximately 30–40°C/W. At the device's typical power consumption (estimate 1.5–2.5W at full load across 10 × 1 Gbps SGMII links), junction temperature rise above ambient can be 50–100°C. An ambient of 55°C with 2W dissipation and θJA = 40°C/W gives Tj = 55 + 80 = 135°C — well above the 85°C maximum junction temperature even with an I-Temp part. I-Temp qualification means the silicon is characterized to work at 85°C junction; it does not replace thermal management. Ensure adequate airflow or thermal spreading to keep Tj below the rated maximum.

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6.0 Modern Substitutes and Upgrade Paths

The 98DX107 is a mature product. For new designs where the 98DX107's feature set is adequate but a newer silicon option is preferred for lifecycle reasons, the natural upgrade path within Marvell's Prestera family is:

Same port count, higher performance: The 98DX240 (Prestera-DX240) and 98DX253 (Prestera-DX253) are 24-port L2/L3 SGMII devices in BGA packages. They offer roughly 2.5× the port density with updated silicon (smaller process node, lower power), but require a BGA PCB design and do not fit the 128-LQFP footprint.

Direct functional equivalent with updated silicon: Marvell's more recent Prestera lineup (98DX25xx series, 98DX35xx) covers 24-port to 48-port configurations. For a direct 10-port L2/L3 equivalent in a smaller footprint with modern process node, the search requires consulting Marvell's current product selector — the 98DX107 slot in the 10-port L2/L3 space may be covered by a more recent 98DX device. Check Marvell's current Prestera product selector guide at marvell.

Alternative vendors:

• Microchip KSZ9897R: 7-port GE switch with integrated PHYs and L2 managed features. Smaller port count but higher integration (no external PHYs needed).
• Realtek RTL9302: 10-port SGMII L2/L3 switch in active production. Comparable port count. Note: Linux kernel driver support for Realtek's switch family is less mature than Marvell's Prestera DSA driver.
• Broadcom BCM53134: 8-port managed GbE switch. L2 focus, integrated PHYs on some variants.

When NOT to upgrade: If the existing design uses the 98DX107 with a validated Linux kernel driver, production-tested reference hardware, and a known-good BSP (Board Support Package), migrating to newer silicon requires rebuilding the entire software stack. For designs already in production or with short remaining product life cycles, the cost of this migration rarely justifies the benefit of newer silicon.

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7.0 PCB and System Integration Notes

LQFP routing: The 128-LQFP package is lead-frame based (not BGA) — signals exit on all four sides of the 14 × 20 mm body. Route high-speed SGMII differential pairs (1.25 Gbps each, 100 Ω differential impedance) with matched length pairs (within 5 mil) and avoid 90° bends. Keep SGMII traces away from digital control signals and power plane edges.

Power supply: The 98DX107 requires multiple supply rails; the exact voltages are in the device datasheet. Typical requirements include a core digital supply (1.2V or 1.8V depending on revision), I/O supply (3.3V), and analog reference. Use dedicated LDO or switching regulators per supply domain with adequate bulk and high-frequency bypass capacitance at each power pin cluster.

Management CPU interface: The management CPU connects to the 98DX107 through MDC/MDIO for PHY register access, and through a higher-bandwidth interface (typically a dedicated MII or SPI port in some variants) for switch register access and packet injection/extraction. In Linux DSA implementations, the CPU appears as a "host" port on the switch fabric, receiving management frames and injecting CPU-originated frames through a designated SGMII or RGMII CPU port.

Clock: The 98DX107 requires a system reference clock input. Typically a 125 MHz oscillator is used. This clock must meet the device's jitter specification — use a low-jitter LVDS or LVTTL oscillator, not a derived clock from a PLL with high phase noise.

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8.0 Sourcing 98DX107-B0-LKJ1I000

The 98DX107 is an active Marvell product but is sourced primarily through Marvell's authorized distribution channel (Avnet, Arrow) for volume customers with a Marvell product agreement. The part is also available through independent component distributors. Given the age of the device, the secondary market contains substantial inventory, but counterfeit risk in the secondary market for enterprise networking silicon is real.

The I-Temp variant (98DX107-B0-LKJ1I000) commands a premium over the commercial-temp variant (98DX107-B0-LKJ1C000) — verify the temperature suffix on received parts. Under-the-hood, a commercial-temp part relabeled as I-Temp may pass bench testing at room temperature but fail at −25°C or +80°C junction temperatures under actual system load.

For verified authentic Marvell 98DX107-B0-LKJ1I000 inventory with full traceability, visit aichiplink.com.

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9.0 Real Questions from Network Hardware Designers

Q: We are designing a 10-port managed gigabit switch with 8 copper RJ-45 ports and 2 SFP fiber uplinks using the 98DX107. The Linux DSA driver is configured but inter-VLAN routing (L3 hardware offload) is not working. Packets are being routed but at CPU speed only. What is required?

A: Hardware L3 offloading requires explicit activation in the Prestera DSA driver and depends on kernel version. First verify that your kernel is 5.15 or later — the Prestera driver's L3 hardware offload support was substantially improved in the 5.15–6.0 series. Second, in RouterOS-based designs (MikroTik), hardware offloading must be enabled per-bridge with the hw=yes flag and the bridge must use VLAN filtering. In custom Linux designs using the upstream DSA driver, ensure the driver is compiled with L3 offload support and that the routing table entries are being installed in hardware (check /sys/class/net/lan0/statistics/ for hardware-offloaded byte counters versus software path). Third, verify that the CPU interface port on the 98DX107 is correctly configured — in DSA topology, the CPU port must be identified correctly in the device tree description or the driver's port enumeration. Misconfigured CPU port mapping is a common cause of packets falling back to software routing.

Q: Can the 98DX107-B0-LKJ1I000 be used at ambient temperatures above 70°C (such as inside a sealed industrial enclosure)?

A: The I-Temp suffix guarantees junction temperature operation to +85°C — not ambient. In a sealed enclosure at 70°C ambient, the actual junction temperature depends on the device's power dissipation and the θJA of the LQFP package in still air (approximately 35–45°C/W). At 2W dissipation and θJA = 40°C/W: Tj = 70 + 80 = 150°C — significantly above the 85°C junction maximum. For sealed industrial enclosures where ambient regularly exceeds 50°C, active thermal management (heat spreader on the LQFP package, conductive cooling through PCB copper, forced airflow via a small fan) is required to keep junction temperature within specification. The I-Temp qualification provides operational margin for temperature variation and cold-start conditions; it does not eliminate the need for thermal design at elevated ambient.

Q: MikroTik's CRS-series routers use Marvell Prestera chips. Does the 98DX107 specifically appear in any MikroTik product?

A: MikroTik's CRS-series switch routers use various generations of Marvell Prestera silicon. The 98DX107 (or closely related DX-series chips) powers several earlier CRS models that feature 10-port GE configurations. MikroTik does not always publicly disclose the exact chip model in each product, but teardowns and RouterOS chip identification strings reveal Prestera DX-series silicon in multiple CRS models including early CRS125 and CRS109 configurations. The Marvell Prestera DSA driver in RouterOS corresponds directly to the same Linux kernel driver — MikroTik's Prestera support effectively validates the open-source driver implementation for these chips at production scale, which is part of why the 98DX107 has maintained strong Linux ecosystem support relative to alternative switch chips of the same era.

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10.0 Quick Reference Card

Part Number Decode:

Field	Value	Meaning
Marvell prefix	98	Prestera enterprise packet processor
Series	DX	Prestera DX switching family
Device	107	10-port GE L2/L3, 4K MAC, 8K routing
Revision	B0	Silicon step B, stepping 0
Package	LKJ	128-pin LQFP, 14mm × 20mm
Variant	1	Sub-variant within LKJ group
Temp grade	I	Industrial: −40°C to +85°C Tj
Distribution	000	Standard commercial

Key Specifications:

Parameter	Value
Ports	10
Interface	10× SGMII (no integrated PHY)
Layer	L2 + L3
MAC table	4,096 entries
Routing table	8,192 IPv4 entries
Process node	0.15 µm
Package	128-LQFP, 14 × 20 mm
Temperature	−40°C to +85°C Tj (I-Temp)
Linux driver	Prestera DSA (mainline kernel)
Eval board	DB-DX107-10G

Critical difference from Link Street (88E6020): 98DX107 = no integrated PHY — all 10 ports need external GE PHY chips or SFP modules. 88E6020 = 2 integrated PHYs included.

98DX107 vs 98DX106:

	98DX107	98DX106
Layer	L2 + L3	L2+ only
MAC table	4K	256 entries
Routing table	8K	None
Description	Multilayer	SecureSmart

When 98DX107 remains the right choice: Validated Linux BSP needed, industrial temperature required, production design with existing RD-DX107 reference circuit, L3 hardware routing needed in 128-LQFP form factor.

When to consider upgrading: New design start, lifecycle concerns about 0.15µm supply continuity, higher port count needed, newer silicon features required.

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Written by Jack Elliott from AIChipLink.

 

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