In the complex architecture of high-speed data center switches, the path between the main switch ASIC (like a Trident or Tomahawk) and the front-panel ports is critical. Signals degrade over long PCB traces, picking up noise and jitter. This is where the Broadcom BCM82328B1KFSBG steps in.
As a 28nm Dual 40GbE / Octal 10GbE Retimer, this chip is the unsung hero that ensures your 40G QSFP+ and 10G SFP+ ports run error-free. While the industry buzzes about 400G and 800G, the BCM82328 remains a vital component for maintaining and building mature, reliable 10G/40G networking infrastructure.
This guide explores the technical specifications, architecture, and sourcing considerations for the BCM82328B1KFSBG.
Table of Contents
- 1. Decoding the Silicon: BCM82328B1KFSBG Specs
- 2. Architecture: XLAUI to XLPPI Bridge
- 3. Configuration Modes: 40GbE vs. 10GbE
- 4. Comparison: BCM82328 vs. BCM82332
- 5. Conclusion
1. Decoding the Silicon: BCM82328B1KFSBG Specs
The BCM82328 is designed using 28nm CMOS technology, offering a balance of performance and power efficiency that defined the mature 40G era.
Key Specifications Matrix
| Feature | Specification | Impact |
|---|---|---|
| Port Configuration | Dual 40GbE or Octal 10GbE | Flexible usage for QSFP+ or SFP+ breakout. |
| Modulation | NRZ (Non-Return-to-Zero) | Standard signaling for 10G/40G legacy links. |
| Host Interface | XLAUI / RXAUI | Connects seamlessly to Switch ASICs. |
| Line Interface | XLPPI / SFI | Drives the optics directly with high drive strength. |
| Process Node | 28nm CMOS | Low power consumption (<1W per 10G equivalent). |
| Package | 19x19mm BGA | "KFSBG" indicates RoHS Compliant / Green. |
Understanding the "B1" Revision & Package
- B1 Revision: In semiconductors, silicon revisions (A0, B0, B1) matter. "B1" typically indicates a mature stepping with fixed errata, ensuring higher stability than initial "A" versions. It is the preferred revision for long-term maintenance.
- KFSBG:
- K: Commercial Temperature range (0°C to 70°C).
- FS: Fine-pitch BGA package.
- BG: "Green" (RoHS/Halogen-free).
Price Analysis & Stock Availability
As a legacy 40G component, the BCM82328 is critical for repairing older line cards or building cost-effective edge switches.
Procurement Tip: Sourcing older Broadcom silicon requires verified channels. [Check Stock for BCM82328B1KFSBG at Aichiplink] to view inventory from trusted distributors.
2. Architecture: XLAUI to XLPPI Bridge
The primary job of the BCM82328 is to bridge the gap between the System Side (ASIC) and the Line Side (Optics).
Signal Integrity: Why Retimers Matter
On a large 48-port switch, the electrical traces from the central ASIC to the ports on the edge can be long (10-20 inches).
- Without Retimer: High-speed 10G/40G signals (NRZ) attenuate and collect jitter over copper traces, leading to bit errors (BER).
- With BCM82328: The chip sits close to the optical cages. It receives the noisy signal, recovers the clock (CDR - Clock Data Recovery), cleans the data (Equalization), and re-transmits a pristine signal to the optical module. This allows designers to use longer PCB traces and cheaper board materials.
3. Configuration Modes: 40GbE vs. 10GbE
The BCM82328 is highly versatile, supporting mixed-mode operations via firmware configuration (MDIO).
Dual 40G Mode (QSFP+)
In this mode, the chip handles two full 40GbE ports.
- It takes 4 lanes of 10G XLAUI from the host and drives 4 lanes of 10G XLPPI to the QSFP+ module.
- Application: Ideal for Top-of-Rack (ToR) switches aggregating server traffic.
Octal 10G Mode (SFP+)
In this mode, the chip drives eight independent 10GbE ports.
- It uses SFI signaling to drive SFP+ modules directly.
- Application: Perfect for high-density 10G line cards where port density is key.
4. Comparison: BCM82328 vs. BCM82332
Engineers often confuse these two similar-looking Broadcom PHYs. It is crucial to choose the right one.
| Feature | BCM82328 (This Chip) | BCM82332 |
|---|---|---|
| Primary Focus | 40G / 10G Retimer | 100G Gearbox & Retimer |
| Max Capability | 2x 40GbE Ports | 1x 100GbE Port (Gearbox) |
| Gearbox Function | No (Retimer mostly) | Yes (10:4 Gearbox for 100G) |
| Typical Use | QSFP+ / SFP+ Switches | QSFP28 100G Line Cards |
| Signaling | 10G NRZ Lanes | 10G & 25G NRZ Lanes |
Verdict:
- If you are designing for QSFP+ (40G), use the BCM82328.
- If you need to convert 10 lanes of 10G (CAUI-10) into 4 lanes of 25G (CAUI-4) for QSFP28 (100G), you need the BCM82332.
5. Conclusion
The Broadcom BCM82328B1KFSBG is a cornerstone of the 10G and 40G Ethernet ecosystem. Its reliability as a retimer makes it indispensable for ensuring data integrity in enterprise switches and routers. While not a 400G powerhouse, it remains a critical part for maintaining the vast installed base of NRZ infrastructure.
Sourcing Legacy Broadcom PHYs Keep your network hardware running. Visit Aichiplink.com to search for BCM82328B1KFSBG and other essential networking ICs.
Written by Jack Elliott from AIChipLink.
AIChipLink, one of the fastest-growing global independent electronic components distributors in the world, offers millions of products from thousands of manufacturers, and many of our in-stock parts is available to ship same day.
We mainly source and distribute integrated circuit (IC) products of brands such as Broadcom, Microchip, Texas Instruments, Infineon, NXP, Analog Devices, Qualcomm, Intel, etc., which are widely used in communication & network, telecom, industrial control, new energy and automotive electronics.
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Frequently Asked Questions
Can the BCM82328 support 100G?
**No.** Not as a 100G gearbox. While it might handle 10 lanes of 10G (SR10 legacy 100G), it lacks the 25G SerDes lanes required for modern 100G QSFP28 (4x25G) modules. For 100G QSFP28, look at the **BCM82793** or **BCM82332**.
Is this chip PAM4 compatible?
**No.** The BCM82328 uses **NRZ (Non-Return-to-Zero)** modulation. PAM4 is utilized in newer 50G/100G/400G generations (like Tomahawk 3/4 chips).
What is the power consumption?
As a 28nm device, it is "low power" for its class, typically consuming **<1W per 10G port** equivalent, making it thermally efficient for dense 1U switches that rely on fan cooling.
Does it require an external clock?
Yes, high-speed PHYs typically require a precise, low-jitter reference clock input (typically 156.25 MHz) to drive the CDR circuits and lock onto the data stream.
