88E6020-B1-NNC2C000: Marvell 4-Port FE Switch Guide

What Is 88E6020-B1-NNC2C000? Why Engineers Still Pick 100 Mbps Over Gigabit in 2025

The reflexive assumption is that gigabit is always better. Gigabit costs nearly the same as Fast Ethernet in switch silicon now. Why would any engineer in 2025 choose a 4-port 100 Mbps switch over a 4-port gigabit switch for a new design?

Several good reasons, and the 88E6020-B1-NNC2C000 illustrates all of them. Industrial sensors, building automation nodes, PLC interfaces, IP camera local switches, and low-bandwidth IoT aggregators do not need gigabit throughput — their traffic budgets are measured in kilobits or low megabits per second. What they do need is a switch that consumes 0.3 watts, costs under two dollars in volume, fits in a 9 × 9 mm QFN-64 footprint, includes IEEE 802.3az Energy Efficient Ethernet to drop power further when links are idle, runs a 1,000-entry MAC table reliably, and provides Virtual Cable Tester diagnostics so a maintenance engineer in the field can check cable integrity without a dedicated instrument.

The 88E6020-B1-NNC2C000 is Marvell's Link Street family entry for this exact use case. Understanding what the part number encodes, how EEE actually works at the silicon level, and what distinguishes the 88E6020's 2+2 port topology from the 5-PHY variants that sit above it in the same family gives engineers the information they need to make the right selection — or to know when to move up to a more capable part.

1.0 Full Part Number Decoded: 88E6020-B1-NNC2C000

Marvell's ordering part number for the 88E6020 switch family encodes silicon revision, package, temperature grade, and regional classification in the suffix characters. Here is the complete decode:

88 — Marvell device family prefix (all Marvell networking devices use 88xx)

E — Ethernet product category (as opposed to storage, wireless, etc.)

6020 — Product identifier within the Link Street Fast Ethernet switch family. The 6020 occupies the 4-port slot in the hierarchy: 88E6020 (4-port) → 88E6070/71 (5-port) → 88E6085 (10-port)

-B1 — Silicon revision:

• B = Die revision B (minor silicon change from revision A; typically bug fixes or performance improvements)
• 1 = Sub-revision 1 within the B generation This field is critical for production designs — boards should specify a minimum silicon revision in procurement documents to ensure they receive the corrected silicon rather than earlier steppings that may have known errata.

-NNC2C000 — Package and qualification suffix:

• N (first) = Package body material code (plastic)
• N (second) = No special marking variant
• C = Commercial temperature grade (0°C to +70°C junction temperature)
• 2 = Package variant code (64-pin QFN, 9 mm × 9 mm body)
• C = Commercial grade qualification
• 000 = Regional/distribution suffix (standard commercial)

Industrial temperature note: The 88E6020 product selector lists industrial temperature grade ("I-Temp", −40°C to +85°C) as "TBD" in Marvell's documentation, meaning the industrial grade variant was either not released or released under a different ordering code. For industrial temperature applications requiring guaranteed −40°C operation, verify with Marvell's distribution network whether an I-Temp variant (which would carry an "I" in the temperature field position rather than "C") is available and qualified, or evaluate the 88E6071 which is listed as supporting industrial temperature.

What the part number does not tell you: The management interface type (MDC/MDIO standard) and the specific MII/RMII port configuration are fixed in the silicon — all 88E6020-B1-NNC2C000 units have the same 2-integrated-PHY + 2-MII/RMII topology. There are no configuration-dependent ordering variants within this specific part number.

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2.0 Specifications: What the 88E6020 Actually Contains

From Marvell's product selector guide and Link Street family documentation:

Switch fabric:

• Total ports: 4 (logical switch ports)
• Switching capacity: Non-blocking at 10/100 Mbps (wire-speed switching across all 4 ports simultaneously)
• MAC address table: 1,024 entries (1K), with configurable aging
• Packet buffer: 64 KB integrated frame memory
• QoS: 4 priority queues per port, 802.1p and port-based classification

Port configuration (2+2 topology):

• 2 ports with integrated PHY: Full 10BASE-T / 100BASE-TX physical layer, Auto-MDI/MDIX, Auto-negotiation
• 2 ports as MII or RMII: External MAC interface for connection to a host processor or CPU MAC, configurable as MII or RMII

Standards compliance:

• IEEE 802.3 10BASE-T
• IEEE 802.3u 100BASE-TX
• IEEE 802.3az EEE (Energy Efficient Ethernet)
• IEEE 802.1p priority queuing
• Port-based VLAN (static, not 802.1Q tagged VLAN)

Diagnostics:

• VCT™ (Virtual Cable Tester): Time-domain reflectometry for cable open/short detection and cable length estimation, accessible via MDC/MDIO registers

Management:

• MDC/MDIO (IEEE 802.3 clause 22/45) for register access and configuration
• No dedicated CPU or embedded management stack — external host accesses switch registers via MDIO through the MII/RMII port's MDIO lines

Power:

• Total power consumption: 0.3W (typical, all ports active at 100 Mbps)
• Supply voltage: 3.3V
• EEE active power reduction: Up to ~80% reduction per port when link is idle (see Section 3)

Package:

• 64-pin QFN (Quad Flat No-lead)
• Body: 9 mm × 9 mm
• 0.5 mm ball pitch (QFN pad pitch)
• Exposed thermal pad on bottom

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3.0 How IEEE 802.3az EEE Works — and Why 0.3W Matters

IEEE 802.3az Energy Efficient Ethernet addresses a fundamental inefficiency in traditional Ethernet: the PHY circuitry must remain active and continuously transmitting idle signal to maintain link synchronization, even when no data frames are being exchanged. On a traditional Fast Ethernet link, maintaining synchronization consumes roughly the same power whether the link is transmitting data at 100 Mbps or sitting completely idle between frames.

EEE introduces a Low Power Idle (LPI) state. When neither end of a link has frames to transmit, both sides can negotiate to enter LPI. During LPI, the transmitter stops sending continuous idle signal and the receiver gates down its signal processing. The link does not fully disconnect — both sides maintain enough state to rapidly wake up — but power consumption in LPI drops to a small fraction of active state.

The wakeup mechanism: When a frame arrives for transmission on an EEE-capable link in LPI, the transmitter sends a short wake signal (a specific set of IDLE symbols defined in 802.3az). The link wakes in approximately 30 µs for 100BASE-TX. If the wake latency is acceptable for the application, the EEE savings are substantial for any link that spends significant time idle.

Power savings calculation for 88E6020:

An integrated PHY at 100 Mbps with no EEE consumes approximately 200–250 mW per port in typical operation (this is the dominant term in the 0.3W total for 4 ports, which includes switch fabric and logic). EEE-capable PHYs reduce active-link power by entering LPI during inter-frame gaps and longer idle periods. The JEDEC/IEEE 802.3az specification targets power reductions of 50–80% under typical office-network-type traffic patterns (which are bursty and have substantial idle time).

For an embedded IoT device with 4 LAN ports where external sensors or network nodes transmit only when data changes (common in industrial monitoring): if each port is active (transmitting or receiving) only 5% of the time, EEE can reduce per-port PHY power from ~200 mW to roughly 40–50 mW. Across 4 ports, this takes per-port total from 800 mW to approximately 160 mW — a significant saving in a battery-adjacent or thermally-constrained design.

This is the quantitative answer to "why not just use gigabit?" A 4-port gigabit switch with integrated PHYs typically consumes 1–2W. For a sensor hub or industrial node that needs Ethernet switching but whose bandwidth requirement is 2–10 Mbps total, the 88E6020's 0.3W profile plus EEE savings is not a compromise — it is the correct engineering choice.

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4.0 The 2+2 Port Topology: Understanding the MII/RMII Uplink Architecture

The 88E6020's 4-port architecture is not symmetrical. Two ports contain fully integrated PHY transceivers — the analog front-end that drives the RJ-45 cable directly. The other two ports are MAC-only interfaces that connect to an external MAC (typically a CPU or host processor's Ethernet controller) using either MII or RMII electrical interfaces.

Why this matters for system design:

In a typical embedded system using the 88E6020:

• The 2 integrated-PHY ports connect directly to RJ-45 connectors through magnetics (Ethernet isolation transformers). These are the user-facing LAN ports.
• The 2 MII/RMII ports connect to the host processor (SoC, microcontroller, or embedded CPU) that manages the switch. The host CPU's MAC sends and receives frames through these ports, and also accesses the switch's MDC/MDIO management registers.

This creates a topology where the host CPU is effectively a "port" in the switch fabric, giving it direct access to all traffic on the switch. This is how managed switch functionality (VLAN configuration, QoS policy, MAC table inspection) is implemented without embedding a management CPU in the switch silicon itself.

MII vs RMII — which to use:

MII (Media Independent Interface): 16-pin interface (4 data pins TX, 4 data pins RX, clocks, control). Runs at 25 MHz for 100 Mbps. Requires a 25 MHz reference clock. Simpler to route but uses more pins.

RMII (Reduced MII): 8-pin interface (2 data pins TX, 2 data pins RX, clocks, control). Runs at 50 MHz. Requires a 50 MHz reference clock (more critical to route cleanly). Fewer pins, smaller footprint.

For most embedded designs with tight BGA-to-PCB routing, RMII is preferred. The 88E6020 supports both on its two external MAC ports, configured by a strap pin or register at initialization.

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5.0 Four Misconceptions About This Part

Misconception 1: "A 100 Mbps switch is obsolete and should always be replaced by gigabit"

This conflates bandwidth with system requirements. The 88E6020 is not used in designs where 100 Mbps is a bottleneck — it is used in designs where 100 Mbps is more than sufficient and the design priorities are power (0.3W vs 1–2W for gigabit), thermal envelope, PCB area (9×9mm vs larger gigabit packages), and BOM cost. Industrial automation nodes, IP intercoms, building control systems, and power line monitoring equipment routinely operate with sub-10 Mbps aggregate traffic. Selecting gigabit for these applications adds cost, power, and thermal challenge without any functional benefit. The 88E6020 is current-production silicon precisely because its use case remains active.

Misconception 2: "Port-based VLAN in 88E6020 is equivalent to 802.1Q tagged VLAN"

The 88E6020 implements port-based VLAN, which partitions the switch fabric by port membership — frames from ports in one VLAN group are not forwarded to ports in a different group, even if they share the same MAC address space. This provides basic traffic isolation without any packet header modification. IEEE 802.1Q tagged VLAN is a different mechanism that inserts a 4-byte VLAN tag into Ethernet frames, allowing VLAN membership to traverse multiple switches and be programmed per-frame. The 88E6020 does not support 802.1Q tagged VLANs — if 802.1Q is required for integration into a managed enterprise network or for multi-switch VLAN spanning, a different device (such as the 88E6061 or higher) is necessary.

Misconception 3: "VCT replaces a cable tester"

Marvell's Virtual Cable Tester uses Time-Domain Reflectometry (TDR) to detect impedance discontinuities on the cable attached to an integrated PHY port. It can identify open circuits, short circuits, and estimate the distance to a fault with reasonable accuracy. What it cannot do: measure insertion loss, verify return loss to TIA-568 specification, characterize near-end or far-end crosstalk, or certify a cable installation to any wiring standard. VCT is a field diagnostic tool — useful for confirming that a cable is physically intact and estimating its length (which can help differentiate "cable too long" from "link autonegotiation failure"). It is not a replacement for an Ethernet cable certification tester (Fluke DTX, Ideal Networks R150, etc.).

Misconception 4: "The 88E6020 can be managed without a host CPU via SNMP or web interface"

The 88E6020 has no embedded management processor, no TCP/IP stack, no SNMP agent, and no web server. It is a Layer 2 unmanaged-to-lightly-managed switch whose configuration is entirely register-based, accessed exclusively through the MDC/MDIO interface from an external host processor. "Managed" in the 88E6020 context means the host CPU can read and write switch configuration registers — it does not mean the switch has any autonomous management capability. If a self-contained managed switch with web/SNMP management and no host CPU is needed, look at devices with embedded ARM cores such as the Microchip KSZ9897R or similar devices with integrated management processors.

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6.0 Application and Design Notes

Reference design: Marvell's evaluation board for the 88E6020 family is the DB1-88E6071-1, which covers the 88E6071 but also documents the reference circuit topology applicable to the 88E6020. The circuit approach is nearly identical.

Magnetics selection: Each integrated PHY port requires a 10/100BASE-TX isolation transformer (Bob Smith termination recommended for EMI reduction). Use a 1:1 ratio transformer with common-mode choke. Suitable devices include Pulse Electronics HX1188NL or Würth Elektronik 749010010A series.

Power supply decoupling: The 88E6020 requires 3.3V. Place 10 µF bulk capacitance and 100 nF high-frequency bypass within 2 mm of each VDD power pin. The analog PHY supply pins (AVDD) are most sensitive to noise — prioritize low-ESR bypass on these pins.

Crystal reference: A 25 MHz crystal is required for the switch fabric timing. Use a ±20 ppm or better crystal with load capacitors per the reference design. Alternatively, a 25 MHz oscillator (LVTTL) can be used if board-level clock distribution already provides 25 MHz.

MDIO configuration: The MDC/MDIO interface uses clause 22 register addressing. The switch appears on the MDIO bus at PHY addresses 16–31 (configurable via strap pins). Each internal port of the switch has its own PHY address on the MDIO bus, so the host CPU can individually configure each port's autonegotiation settings, read link status, and trigger VCT diagnostics on a per-port basis.

Linux driver integration: The 88E6020 is supported in the Linux kernel through the DSA (Distributed Switch Architecture) framework. The driver mv88e6xxx handles the Marvell Link Street switch family including 88E6020. On platforms running Linux (embedded SoC with RMII connecting to 88E6020), the switch appears as a set of individual network interfaces (e.g., lan0, lan1) that the kernel can route between, bridge, or apply iptables rules to.

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7.0 Real Questions from Network Embedded Designers

Q: My 88E6020 is connected via RMII to a Cortex-M7 microcontroller. After link-up, I see correct MAC statistics on the switch registers but no frames appear on the host MCU's Ethernet driver. What is likely wrong?

A: The most common cause is an RMII clock phase or reference clock issue. RMII requires a 50 MHz reference clock shared between the MAC (MCU) and the PHY/switch. In the 88E6020, the RMII reference clock is typically provided by the host — verify that the MCU is generating a clean 50 MHz RMII clock and that it is correctly routed to the 88E6020's RMII reference clock input. Verify the clock meets the 88E6020's input clock specifications (rise/fall times, duty cycle). Second common cause: RMII data sampling direction. RMII has a specific setup/hold relationship between the reference clock and the data lines — if the MCU's RMII interface samples on the wrong clock edge, frames will be corrupted or absent. Check the MCU's RMII configuration register for clock edge selection. Third: verify the 88E6020 RMII port is configured as a MAC interface (not a PHY interface) in its port type register — the default may require explicit configuration via MDIO before RMII traffic flows correctly.

Q: We need 802.1Q tagged VLAN support for integrating with our campus LAN infrastructure. Can the 88E6020 be configured for this?

A: The 88E6020 does not support IEEE 802.1Q tagged VLAN — it supports port-based VLAN only, which provides traffic isolation between port groups but does not insert or process 802.1Q VLAN tags. For 802.1Q support in the Marvell Link Street family, look at the 88E6061 or 88E6063 which include 802.1Q tagged VLAN capability. If the application only needs to isolate traffic between the two integrated-PHY ports (keeping them independent rather than bridged) without 802.1Q header modification, the 88E6020's port-based VLAN is sufficient.

Q: Can the VCT cable length measurement be triggered from Linux without writing custom kernel code?

A: Yes. The mv88e6xxx Linux DSA driver includes ethtool support, and ethtool provides a cable test interface. Run ethtool --cable-test lan0 (substituting your actual interface name) on a system using the mv88e6xxx driver to trigger VCT on the corresponding port. The result reports whether the cable is open, short, or OK, and an estimated distance to the fault if one is detected. The --cable-test-tdr option on newer kernel versions provides the raw TDR amplitude profile if more detailed analysis is needed. This functionality requires kernel 5.10 or later with the full DSA ethtool cable test interface merged; on older kernels, direct MDIO register access via mdio-netlink or a custom diagnostic tool may be required.

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8.0 Quick Reference Card

Part Number Decode:

Field	Value	Meaning
Family	88E	Marvell Ethernet
Device	6020	4-port Fast Ethernet switch
Revision	B1	Silicon step B, sub-revision 1
Pkg/material	NN	Plastic, standard marking
Temp grade	C	Commercial (0°C to +70°C Tj)
Package	2	64-pin QFN, 9×9mm
Qualification	C000	Commercial / standard distribution

Key Specifications:

Parameter	Value
Total ports	4
PHY ports	2 (integrated 10/100BASE-TX)
Uplink ports	2 (MII or RMII, configurable)
Max speed	100 Mbps per port
Switch fabric	Non-blocking at wire speed
MAC address table	1,024 entries
Packet buffer	64 KB
QoS queues	4 per port
EEE standard	IEEE 802.3az
Total power	0.3W typical
Supply voltage	3.3V
Package	64-QFN, 9mm × 9mm
Diagnostics	VCT™ (cable TDR)
Linux driver	mv88e6xxx (DSA framework)

The 2+2 Topology in One Line:
2 ports → RJ-45 (integrated PHY)
2 ports → Host CPU (MII or RMII MAC interface)

When 88E6020 is the right choice: Total system bandwidth < 20 Mbps, power budget < 0.5W, PCB space constrained, IEC 62443/industrial environment, basic traffic isolation needed without 802.1Q

When to use a different part: 802.1Q tagged VLAN required → 88E6061/63; 5+ user-facing ports → 88E6071; industrial temperature (−40°C) confirmed → verify I-Temp variant; gigabit speeds needed → 88E6352 or similar

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Written by Jack Elliott from AIChipLink.

 

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