QCA8337-AL3C: 7-Port GbE Switch Complete Design Guide

QCA8337-AL3C: The "7-Port" Switch Where Understanding Which 2 Ports Matter Most Is the Entire Design Challenge

The QCA8337 is marketed as a 7-port Gigabit Ethernet switch. The description is accurate but incomplete in a way that consistently surprises engineers encountering it for the first time: those 7 ports are not interchangeable. Five of the ports are standard user-facing Ethernet ports with integrated PHY transceivers — connect a cable, get a gigabit link. The other two ports are CPU uplink ports: they connect the switch fabric to the host processor or SoC via SGMII or RGMII electrical interfaces, not to Ethernet cables.

The CPU port selection determines the entire throughput architecture of the system. A router or gateway built around QCA8337 has one path for all traffic to reach the CPU: the CPU port. If the CPU port is RGMII at 1 Gbps, and three ports are simultaneously pushing 1 Gbps each, the CPU port is a bottleneck — 3 Gbps of switch traffic competing for 1 Gbps of uplink bandwidth. If the design uses the SGMII interface (which the QCA8337 supports), the available bandwidth profile changes. If the design uses both CPU port connections (the QCA8337 supports dual CPU ports), the aggregated uplink bandwidth doubles.

The five integrated PHY ports are the simple part. The CPU port design — which interface, which connection, which driver configuration — is where QCA8337 designs succeed or encounter throughput limitations that are difficult to debug without understanding the port architecture.

1.0 Part Number Decoded: QCA8337-AL3C

Qualcomm's (formerly Atheros) switch IC ordering part numbers encode the product family, temperature grade, package, and packaging format:

QCA — Qualcomm Atheros product prefix (used across Qualcomm's Atheros-heritage networking portfolio acquired from Atheros Communications in 2011)

8337 — Product identifier within the QCA8xxx switch family:

• 83xx = integrated PHY + switch fabric family (as opposed to QCA85xx which are switch-only with external PHYs)
• 8337 specifically = 7-port variant with 5 integrated GE PHYs + 2 CPU ports
• Sibling variants: QCA8334 (4-port), QCA8335 (5-port), QCA8327 (earlier 7-port with fewer features)

-A — Silicon revision: A = current production revision (prior revision was pre-production)

L — Temperature grade:

• L = Commercial temperature: 0°C to +70°C junction
• I-grade industrial variants exist for some QCA83xx family members; for QCA8337, verify availability with Qualcomm distribution

3 — Package type code:

• 3 = QFN (Quad Flat No-Lead) package
• The standard QCA8337-AL3C uses a QFN-48 package (48 pins, 7mm × 7mm body)
• Note: QCA8337N-AL3C uses a 148-pin QFN with exposed pad — a different, larger package with more I/O pins available. The "N" in QCA8337N indicates the extended-pin variant.

C — Packaging format: C = Tray (quantity per tray as specified by Qualcomm)

QCA8337-AL3C vs QCA8337N-AL3C:

Parameter	QCA8337-AL3C	QCA8337N-AL3C
Package	QFN-48, 7×7mm	QFN-148 (with exposed pad)
I/O pins	48	148
LED pins	Limited	More LED control pins
Typical use	Compact router/gateway	Higher-density designs needing more GPIO/LED

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2.0 Specifications at a Glance

From Qualcomm's QCA8337 product brief and community-documented specifications (full datasheet under NDA):

Switch fabric:

• Total ports: 7
• User ports (with integrated PHY): 5 × 10/100/1000BASE-T (ports 1–5)
• CPU/uplink ports: 2 (ports 0 and 6) — RGMII or SGMII to host SoC
• Non-blocking switch fabric: wire-speed switching across all 7 ports
• Forwarding rate: up to 14.88 Mpps at 64-byte frames

MAC address table:

• Entries: 2,048 (2K) MAC address table
• Dynamic learning with configurable aging timer
• Static entry support for multicast and management addresses

Management features (Layer 2):

• IEEE 802.1Q VLAN (tagged and port-based)
• IGMP snooping (v1/v2/v3)
• MLD snooping (IPv6 multicast)
• Link aggregation (802.3ad LACP)
• 802.1p QoS: 4 priority queues per port
• DSCP-based QoS classification
• Spanning Tree Protocol (STP/RSTP/MSTP)
• Port mirroring
• Storm control (broadcast/multicast/unknown unicast)
• ACL (Access Control Lists): Flow-based packet classification

CPU interface:

• Port 0: RGMII (to host SoC GMAC 0)
• Port 6: SGMII or RGMII (to host SoC GMAC 1) — selectable via strap/register
• Supports single CPU port (port 0 or port 6) or dual CPU port configuration

Management access:

• MDC/MDIO (IEEE 802.3 Clause 22 and Clause 45)
• Switch registers accessed via pseudo-PHY MDIO address (default: PHY address 0x10 for the switch global registers)
• Qualcomm SSDK (Switch Software Development Kit) for Linux
• Linux kernel DSA driver: qca8k (mainline from kernel 4.x)

Power:

• Core supply: 1.2V
• I/O supply: 1.8V (for 1.8V I/O banks) or 3.3V (for 3.3V I/O banks depending on pin function)
• Analog supply: 1.8V
• Typical power consumption: approximately 2.5–3.5W at full load (all 5 GbE PHY ports active)

Package:

• QFN-48, 7mm × 7mm body, exposed thermal pad
• Operating temperature: 0°C to +70°C junction (commercial, L-grade)

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3.0 Architecture: The 5+2 Port Topology and CPU Port Configuration

Switch fabric overview:

The QCA8337 contains a complete L2 managed switch ASIC with five integrated Gigabit Ethernet PHY transceivers. The five PHY ports (ports 1–5) each contain the full 1000BASE-T analog front-end: twisted-pair line drivers, multi-level signal processing, digital adaptive equalization, echo cancellation, and auto-MDI/MDI-X — exactly the functionality of a standalone GbE PHY chip, but integrated directly into the switch fabric. Each PHY port connects through a set of Ethernet isolation magnetics to an RJ-45 connector.

The two CPU ports (ports 0 and 6) are MAC-only interfaces — they connect to the host processor's Ethernet MAC using RGMII or SGMII electrical signaling, not to Ethernet cables. All user traffic that needs to reach the host CPU (for routing, firewall processing, or management) must transit through one of these CPU ports.

The CPU port bandwidth constraint:

Each CPU port, when configured as RGMII at 1 Gbps, provides 1 Gbps full-duplex (1 Gbps TX, 1 Gbps RX = 2 Gbps aggregate) of connectivity between the switch fabric and the host CPU. If all five user ports are simultaneously handling heavy traffic, the aggregate user-port bandwidth is 5 × 1 Gbps = 5 Gbps — but only 1 Gbps can transit the single CPU port at a time. In most router/gateway workloads, not all ports are saturated simultaneously, and the CPU's processing throughput (not the CPU port bandwidth) is the real bottleneck. For truly high-throughput applications, enabling dual CPU ports (ports 0 and 6 both active) provides 2 Gbps of total CPU uplink bandwidth.

CPU port 0 vs port 6:

In the Linux DSA qca8k driver, the CPU port assignment depends on the device tree configuration. The QCA8337 supports port 0 as the primary CPU port (RGMII, connected to the SoC's first GMAC) and port 6 as a secondary CPU port or as an additional uplink port (SGMII capable). Common configurations in production routers:

• Single CPU port (port 0): Standard for 4-LAN + 1-WAN routers where the WAN port is on the SoC side and 4 LAN ports come from PHY ports 1–4 of the QCA8337
• Dual CPU port (port 0 + port 6): Used for higher-throughput designs or for isolating WAN/management traffic on one CPU port from LAN traffic on the other

Linux DSA integration:

The qca8k driver in the Linux kernel presents the QCA8337 to the operating system as a set of individual network interfaces (e.g., lan1, lan2, lan3, lan4, wan) managed by the DSA (Distributed Switch Architecture) subsystem. The host SoC's GMAC interfaces as the DSA "master" interface. The qca8k driver handles all switch register programming through MDIO, including VLAN configuration, port state, and QoS settings.

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4.0 ⚠️ Four Design Pitfalls with QCA8337-AL3C

Pitfall 1: Confusing the MDC/MDIO PHY bus with the switch register access mechanism

The QCA8337 has two types of MDIO-accessible registers: standard IEEE 802.3 PHY registers (accessible at PHY addresses 0–4 for the five integrated PHYs) and switch global/port registers (accessible via a pseudo-PHY at the switch's management address, typically 0x10). The switch global registers use a non-standard extended MDIO access protocol: a write to register 0x1D (indirect address register) followed by a write or read to register 0x1E (indirect data register). This indirect access mechanism is what the qca8k driver implements. A design that attempts to manage the switch using only standard MDIO PHY register reads/writes will successfully read individual PHY status (link up/down, speed) but will be unable to configure VLANs, QoS, or any switch fabric feature. Verify that the management software uses the indirect register access mechanism, not direct PHY address reads.

Pitfall 2: Incorrect RGMII clock delay configuration for the CPU port

The QCA8337's CPU port RGMII interface has configurable internal clock delay (both TX and RX delay). The delay setting must match what the host SoC's RGMII interface expects. Some SoCs provide the RGMII clock delay on the SoC side; others expect it on the PHY/switch side. Enabling delay on both sides (SoC and QCA8337) doubles the delay and causes RGMII setup/hold timing violations — the CPU port link will appear to come up but will drop packets or show intermittent CRC errors. Verify whether the host SoC already applies RGMII delay, and configure the QCA8337's internal delay via its AT803X_INITMAC register accordingly. In the Linux qca8k driver, this is configured via the device tree rgmii-id, rgmii-rxid, or rgmii-txid phy-mode properties on the CPU port node.

Pitfall 3: Not accounting for the QCA8337's default VLAN configuration at power-up

At power-up without explicit software configuration, the QCA8337 operates in a default VLAN configuration where all 7 ports are in the same broadcast domain. For a router/gateway design where the intended behavior is port isolation (LAN ports do not directly communicate with each other — all traffic goes through the host CPU for routing), this default configuration allows direct LAN-to-LAN switching at wire speed — bypassing the CPU entirely. From a security and functionality standpoint, a router running NAT/firewall requires that LAN client-to-client traffic either goes through the CPU or is deliberately hardware-switched. If the intended behavior is CPU routing between all ports, each port must be configured as an isolated port in a separate VLAN or in a port-based VLAN that forces all traffic through the CPU port. This configuration must be applied by the driver (qca8k handles this automatically for DSA deployments) or by manual SSDK register writes before the switch begins forwarding.

Pitfall 4: Powering the QCA8337 without proper sequencing of the 1.2V and 1.8V rails

The QCA8337 requires the 1.2V core supply to stabilize before the 1.8V I/O supply is applied. Applying 1.8V before or simultaneously with 1.2V can cause the internal logic to enter an undefined state that requires a full power cycle to resolve. On some designs, the power sequencer (or the order of LDO outputs) is not explicitly controlled, and the 1.8V rail races ahead of the 1.2V rail at startup. Symptoms include: the MDIO bus fails to detect the switch (no response to PHY address scans), the switch registers read back unexpected values, or the switch operates erratically until the board is power-cycled. Add an explicit power sequencing circuit or use a PMIC with programmable sequencing to ensure 1.2V is established before 1.8V.

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5.0 Application Design Notes: Power, MDIO, and Linux DSA Integration

Power supply design:

The QCA8337-AL3C requires three supply domains:

• VDD_CORE (1.2V): Digital core logic supply. Current demand: approximately 500–800 mA under full load. Use a dedicated switching regulator capable of ≥1A output. Decouple with 10 µF + 100 nF ceramics at each VDD_CORE pin cluster.
• VDD_IO (1.8V): I/O supply for the RGMII/SGMII interface and switch management signals. Keep this rail clean — RGMII signal transitions couple to the I/O supply, and supply noise here directly appears as jitter on the CPU port interface.
• VDD_REG (3.3V): Used for some internal regulators and analog sections in certain pin configurations. Verify requirements against the QCA8337 reference schematic.

Magnetics for PHY ports:

Each of the five integrated PHY ports (ports 1–5) requires one 10/100/1000BASE-T isolation transformer module between the MDI differential pairs and the RJ-45 connector. Use 1000BASE-T rated magnetics with Bob Smith termination. Place magnetics within 15 mm of the QCA8337's MDI pins.

Device tree configuration for Linux DSA:

A minimal device tree excerpt for QCA8337 with single CPU port on port 0:

&mdio0 {
    switch@10 {
        compatible = "qca,qca8337";
        reg = <0x10>;

        ports {
            port@0 {
                reg = <0>;
                label = "cpu";
                ethernet = <&gmac0>;
                phy-mode = "rgmii-id";
                fixed-link {
                    speed = 1000;
                    full-duplex;
                };
            };
            port@1 { reg = <1>; label = "lan1"; };
            port@2 { reg = <2>; label = "lan2"; };
            port@3 { reg = <3>; label = "lan3"; };
            port@4 { reg = <4>; label = "lan4"; };
            port@5 { reg = <5>; label = "lan5"; };
        };
    };
};

The phy-mode = "rgmii-id" on the CPU port enables both RX and TX internal delay in the QCA8337. Adjust to rgmii-rxid, rgmii-txid, or rgmii depending on what the host SoC provides.

Qualcomm SSDK:

For designs using Qualcomm's own IPQ-series SoCs (IPQ4018, IPQ5018, IPQ8064, etc.), Qualcomm's Switch Software Development Kit (SSDK) provides a userspace management interface to the QCA8337 via an ioctl interface. SSDK is used in Qualcomm's OpenWrt-based reference firmware (QSDK) to configure VLANs, ACLs, and QoS without going through the Linux kernel DSA stack. For custom Linux deployments, the mainline qca8k DSA driver is the recommended approach; SSDK is an alternative for QSDK-based embedded platforms.

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6.0 Comparison: QCA8337 vs QCA8337N and Competing 7-Port Switches

QCA8337-AL3C vs QCA8337N-AL3C:

Parameter	QCA8337-AL3C	QCA8337N-AL3C
Package	QFN-48, 7×7mm	QFN-148 with exposed pad
Die	Same	Same
Feature set	Same	Same
LED pins	Limited	More LED control available
PCB complexity	Lower (fewer pins)	Higher (148-pin QFN)
Typical use	Compact consumer router, gateway	Higher-density with more LED/GPIO

QCA8337 vs Marvell 88E6061 (alternative 7-port managed switch):

Parameter	QCA8337-AL3C	Marvell 88E6061
Ports	5 PHY + 2 CPU	5 PHY + 2 CPU
CPU interface	RGMII + SGMII	RGMII
802.1Q VLAN	Yes	Yes
Linux DSA driver	qca8k (mainline)	mv88e6xxx (mainline)
IGMP snooping	Yes	Yes
ACL	Yes	Limited
Package	QFN-48	BGA/QFP
Ecosystem	IPQ SoC family (Qualcomm)	Marvell/generic

QCA8337 in the broader Qualcomm switch family:

Device	Ports (PHY+CPU)	Notable
QCA8334	4 PHY + 2 CPU	Smaller 4-port version
QCA8337	5 PHY + 2 CPU	Most common in consumer routers
QCA8386	8 PHY + 2 CPU	Larger, higher density
AR8327	5 PHY + 2 CPU	Predecessor; same port count, fewer features

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7.0 Sourcing QCA8337-AL3C

The QCA8337-AL3C is an active Qualcomm production part, available through authorized distribution (Arrow, Avnet, DigiKey) and widely stocked in the secondary market due to its widespread use in consumer networking equipment (home routers, mesh nodes, enterprise access points).

Counterfeit awareness: The QCA8337 is one of the most widely counterfeited Ethernet switch ICs, particularly in the consumer router repair market. Common counterfeits include re-marked QCA8227 (5-port, fewer features) or AR8327 (older generation) chips. Verification method: read the switch's chip ID register via MDIO. The QCA8337's internal ID register at switch management address 0x10, register 0x0000 (Hardware Version) should return a specific value corresponding to QCA8337. The qca8k driver logs this value during probe and aborts if the chip ID does not match a supported device. A counterfeit will either fail MDIO communication entirely or return an incorrect chip ID.

For verified authentic Qualcomm QCA8337-AL3C with competitive pricing and traceability, visit aichiplink.com.

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8.0 Real Questions from Embedded Network Designers

Q: We are designing a 5-port LAN + 1-port WAN router using QCA8337 with a QCA9558 Wi-Fi SoC. Should we use port 0 or port 6 as the CPU port, and how should we configure the WAN port?

A: The QCA9558 has two GMAC interfaces: GMAC0 (RGMII capable) and GMAC1 (SGMII capable). A standard 4-LAN + 1-WAN configuration using QCA8337 is: WAN port on the QCA8337's PHY port 1 (or 5), LAN ports on PHY ports 2–5 (or 1–4), CPU port 0 connected via RGMII to QCA9558 GMAC0. The WAN port is a PHY port on the switch — traffic from the WAN Ethernet connection is received by the switch and forwarded to the CPU via port 0 for NAT/firewall processing before being forwarded out to LAN ports. Port 6 can be left unused or configured as a second CPU port for management isolation. In the device tree, configure VLANs to separate WAN (e.g., VLAN 2 on port 1 and port 0 tagged) from LAN (VLAN 1 on ports 2–5 and port 0 tagged), with the QCA9558 software handling the WAN/LAN routing between VLAN interfaces.

Q: After bringing up the QCA8337, the qca8k driver loads and ports appear, but all LAN clients can directly communicate with each other without going through the CPU — they bypass the router's firewall. What is wrong?

A: This is the default VLAN behavior described in Pitfall 3. Without explicit VLAN isolation, the QCA8337 operates as a flat L2 switch — all ports in one broadcast domain, traffic between LAN ports hardware-switched at line speed without CPU involvement. For a router/firewall design, each LAN port must be in a separate port-based VLAN that forces traffic through the CPU port, or all ports must be in a single VLAN with port isolation enabled (so no port-to-port communication is possible without transiting the CPU). In the qca8k DSA driver with a properly configured device tree (using dsa,member properties and VLAN definitions), the driver automatically configures port isolation so LAN-to-LAN traffic transits the CPU. If you configured the hardware manually without using the full DSA framework, you must explicitly program the QCA8337's port VLAN membership and tagged/untagged VLAN registers to isolate ports. Review the QCA8337 register documentation for the PORT_LOOKUP_CTRL register, which controls which ports can forward to which other ports.

Q: Can QCA8337-AL3C be used for an industrial application at −10°C ambient? The L-grade commercial temperature is 0°C minimum junction.

A: The commercial L-grade is characterized and guaranteed from 0°C junction temperature minimum. At −10°C ambient, with the device dissipating approximately 2.5W in active operation and a θJA of approximately 30°C/W, the junction temperature would be approximately −10°C + (2.5 × 30) = 65°C — well within the 70°C junction maximum. The concern is not the hot end but the cold end: at −10°C ambient with the device cold (before self-heating), the junction temperature starts at approximately −10°C + small self-heating during startup, which is below the 0°C characterized minimum. This may cause initialization issues during cold start. Options: (1) use a board heater to pre-warm the PCB above 0°C before boot; (2) use a slower power-up sequence that allows self-heating to bring the junction above 0°C before full operation; (3) check whether Qualcomm offers an industrial-temperature QCA8337 variant for your volume; (4) evaluate alternative switches with industrial temperature qualification such as the Microchip KSZ9897 or Marvell 88E6361.

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9.0 Quick Reference Card

Part Number Decode:

Field	Value	Meaning
QCA	QCA	Qualcomm Atheros
8337	8337	7-port L2 GbE switch, 5 integrated PHYs
A	A	Silicon revision A
L	L	Commercial: 0°C to +70°C junction
3	3	QFN-48 package (7×7mm)
C	C	Tray packaging

Key Specifications:

Parameter	Value
Total ports	7
User ports (with PHY)	5 (ports 1–5, 10/100/1000BASE-T)
CPU uplink ports	2 (ports 0, 6 — RGMII/SGMII)
Switch fabric	Non-blocking, wire-speed
MAC address table	2,048 entries
VLAN	IEEE 802.1Q + port-based
IGMP snooping	Yes (v1/v2/v3)
QoS queues	4 per port
STP/RSTP	Yes
Core voltage	1.2V
I/O voltage	1.8V / 3.3V
Typical power	~2.5–3.5W (all ports active)
Package	QFN-48, 7×7mm
Temperature	0°C to +70°C
Linux driver	qca8k (DSA, mainline kernel)

Port Architecture at a Glance:

Ports 1–5: Integrated 10/100/1000BASE-T PHY → Magnetics → RJ-45
Port 0:    MAC only → RGMII → Host SoC GMAC0 (CPU port, primary)
Port 6:    MAC only → SGMII or RGMII → Host SoC GMAC1 (CPU port, secondary)

Common Reference Platform Pairings:

• QCA9558 (Wi-Fi 5, MIPS) + QCA8337 → Home router (TP-Link, D-Link, Netgear)
• IPQ4018/IPQ4019 (Wi-Fi 5, ARM) + QCA8337 → AC wave-2 gateway
• IPQ5018 (Wi-Fi 6, ARM) + QCA8337 → AX3000 mesh node
• IPQ8064 (Wi-Fi 5, dual-core ARM) + QCA8337 → Enterprise access point

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Written by Jack Elliott from AIChipLink.

 

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