Microchip SY89871UMG
Manufacturer No:
SY89871UMG
Manufacturer:
Microchip
Package:
16-VFQFN Exposed Pad, 16-MLF®
Description:
2.5GHz Any Diff. IN-to-LVPECL Programmable Clock Divider/Fanout Buffer with Internal Termination
Quantity:
In Stock :8260
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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User Guide
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
SY89871UMG Information
Microchip SY89871UMG technical specifications, attributes, parameters and parts with similar specifications to Microchip SY89871UMG.
- Type
- Parameter
- Description
- 2 Banks (÷1, ÷2, ÷4, ÷8, ÷16); 2 Outputs
- Input
- ANY
- Output
- LVPECL
- Supply Voltage
- 2.5/3.3V
- Max Freq (GHz)
- 2.5
- Icc (mA)
- 50
- Max Within Device Skew (ps)
- \u003c15
- OE
- False
- Input Mux
- False
- Number Of Outputs
- 0
- Type
- Parameter
- Max Prop Delay (ps)
- 670
Download datasheets and manufacturer documentation for Microchip SY89871UMG.
Data Sheets:
User Guide:
The SY89871U is a 2.5V/3.3V
LVPECL output precision clock divider capable of accepting a high-speed
differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock
input signal and dividing down the frequency using a programmable divider ratio
to create a frequency locked lower speed version of the input clock (Bank
B).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz
auxiliary clock components.
The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.
The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.
- Bank A: undivided pass-through (QA)
- Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
- Matched delay: all outputs have matched delay, independent of divider setting
- >2.5GHz fMAX
- <250ps tr/tf
- <670ps tpd (matched delay)
- <15ps within-device skew
- 231fsRMS phase jitter (typ.)
- Power supply 3.3V or 2.5V
- Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
- TTL/CMOS inputs for select and reset
- 100K EP compatible LVPECL outputs
- Parallel programming capability
- Wide operating temperature range: -40°C to +85°C
- Available in 16-pin (3mm x 3mm) QFN package
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
