Microchip SY100EL92ZG

Manufacturer No:

SY100EL92ZG

Manufacturer:

Microchip

Package:

20-SOIC (0.295, 7.50mm Width)

Description:

Triple LVPECL-to-PECL or PECL-to-LVPECL Translators

Quantity:

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In Stock :Available

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SY100EL92ZG information

Microchip SY100EL92ZG technical specifications, attributes, parameters and parts with similar specifications to Microchip SY100EL92ZG.

Type
Parameter

Input
PECL/LVPECL

Output
PECL/LVPECL

Supply Voltage
3.3/ 5/-5

Max Freq (GHz)
0.3

Icc (mA)
12

Max Within Device Skew (ps)
100

OE
False

Input Mux
False

Max Prop Delay (ps)
630

Download datasheets and manufacturer documentation for Microchip SY100EL92ZG.

Application Notes:

28e47621c3774d8713e580970ed13782.pdf

Data Sheets:

13b13aa5cb253d5f8c61560513732d3a.pdf

The SY100EL92 is a triple LVPECL-to-PECL or PECLto-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). SY100EL92 can also be used as a differential line receiver for PECL-to-PECL or LVPECL-to-LVPECL signals. However, please note that for the latter we will need two different power supplies. Please refer to Function Table for more details.V_BB outputs are provided for interfacing single ended input signals. If a single ended input is to be used, the V_BB output should be connected to the D input and the active signal will drive the D input. When used, the V_BB should be bypassed to V_CC via a 0.01µF capacitor.

The V_BB is designed to act as a switching reference for the SY100EL92 under single ended input conditions. As a result, the pin can only source/sink 0.5mA of current.To accomplish the PECL-to-LVPECL level translation, the SY100EL92 requires three power rails. The VCC and VCC_VBB supply is to be connected to the standard PECL supply, the 3.3V supply is to be connected to the VCCOsupply, and GND is connected to the system ground plane.

Both the V_CC and V_CCO should be bypassed to ground with a 0.01µF capacitor.To accomplish the LVPECL-to-PECL level translation, the SY100EL92 requires three power rails as well. The 5.0V supply is connected to the V_CC and V_CCO pins, 3.3V supply is connected to the V_CC_V_BB pin and GND is connected to the system ground plane. V_CC_V_BB is used to provide a proper VBB output level if a single ended input is used. For differential LVPECL input V_CC_V_BB can be either 3.3V or 5V.Under open input conditions, the D input will be biased at a V_CC/2 voltage level and the D input will be pulled to GND. This condition will force the "Q" output low, ensuring stability.

5V and 3.3V power supplies required
Also, supports LVPECL-to-PECL translation
500ps propagation delays
Fully differential design
Differential line receiver capability
Application note
Available in 20-pin SOIC package

User Guide

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