ONSEMI MC100LVEP210FAG

ONSEMI MC100LVEP210FAG

Manufacturer No:

MC100LVEP210FAG

Manufacturer:

ONSEMI

Package:

32-LQFP

Description:

Clock Driver, 1:5 Differential, Dual ECL / PECL / HSTL, 2.5 V / 3.3 V

Delivery:

DHL
DHL
DHL
DHL

Payment:

DHL
DHL
DHL
DHL
DHL
DHL
DHL

In Stock :Available

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MC100LVEP210FAG information

ONSEMI MC100LVEP210FAG technical specifications, attributes, parameters and parts with similar specifications to ONSEMI MC100LVEP210FAG.

  • Type
  • Parameter
  • MSL Temp (°C)
  • 260
  • Type
  • Buffer
  • VCC Typ (V)
  • 3.3
  • Container Type
  • JTRAY
  • Container Qty.
  • 250
  • Input / Output Ratio
  • 1:5
  • Input Level
  • CML
  • fmaxClock Typ (MHz)
  • 3000
  • Package Type
  • LQFP-32
  • Case Outline
  • 561AB
  • MSL Type
  • 2
  • Channels
  • 2
  • Output Level
  • ECL
  • tJitterRMS Typ (ps)
  • 0.207
  • tskew(o-o) Max (ps)
  • 25
  • tpd Typ (ns)
  • 0.35
  • tR & tF Max (ps)
  • 250
  • fmaxData Typ (Mbps)
  • -

Download datasheets and manufacturer documentation for ONSEMI MC100LVEP210FAG.

Datasheet:

Package Drawing:

The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode.The LVEP210 specifically guarantees low output-to-output skew.Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.The MC100LVEP210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP210 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single-ended CLK input operation is limited to a VCC ≤ 3.0 V in PECL mode, or VEE ≤ -3.0 V in ECL mode.Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D.

Feature

  • 85 ps Typical Device-to-Device Skew
  • 20 ps Typical Output-to-Output Skew
  • VBBOutput
  • Jitter Less than 1 ps RMS
  • 350 ps Typical Propagation Delay
  • Maximum Frequency >3 Ghz
  • The 100 Series Contains Temperature Compensation
  • PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • Open Input Default State
  • LVDS Input Compatible

User Guide

PURCHASE

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MEANS OF PAYMENT

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IMPORTANT NOTICE

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Step1：Prepare product

Step1：Prepare product

Step2：Desiccant Protection

Step2：Desiccant Protection

Step3：Vacuum Packaging

Step3：Vacuum Packaging

Step4：Individual Package

Step4：Individual Package

Step5：Anti-collision Filling

Step5：Anti-collision Filling

Step6：Packaging Box

Step6：Packaging Box

SHIPPING COST

1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.

SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

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