ONSEMI MC100EP195FAR2G

Manufacturer No:

MC100EP195FAR2G

Manufacturer:

ONSEMI

Package:

32-LQFP

Description:

3.3 V ECL Programmable Delay Chip

Quantity:

Delivery:

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In Stock :Available

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MC100EP195FAR2G information

ONSEMI MC100EP195FAR2G technical specifications, attributes, parameters and parts with similar specifications to ONSEMI MC100EP195FAR2G.

Type
Parameter

Input Level
CML

td(step) Typ (ps)
14

Package Type
LQFP-32

MSL Type
2

Container Qty.
2000

VCC Typ (V)
3.3

td(prog) Max (ns)
10.95

MSL Temp (°C)
260

Container Type
REEL

td(prog) Min (ns)
7.85

tJitter Typ (ps)
1.16

tR & tF Max (ps)
200

Case Outline
561AB

Output Level
ECL

fMax Typ (MHz)
1200

Download datasheets and manufacturer documentation for ONSEMI MC100EP195FAR2G.

Datasheet:

6f8f2c70c6254f0c041c1dfedc912b9e.pdf

Package Drawing:

344de9a7b11b158d609e7732ce3b1d04.pdf

NECL/PECL input transition.The delay section consists of a programmable matrix of gates and multiplexers as shown in the data sheet logic diagram. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(0:9) which are latched on chip by a high signal on the latch enable (LEN) control. The MC10/100EP195 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in the data sheet.Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Select input pins D0-D10 may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for CMOS, ECL, or TTL level signals. For CMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (pins 7 and 8). For TTL level operation, connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 1.5k Ohm or 500 Ohm resistor between VCF and VEE for 3.3 V or 5.0 V power supplies, respectively. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or

Application

Automated Test Equipement (ATE)
General Purpose Data and Clock Interface

Feature

Maximum Frequency > 1.2 Ghz Typical
Programmable Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range: V_CC = 3.0 V with V_EE = 0 V
NECL Mode Operating Range: V_CC = 0 V with V_EE = -3.0 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the ENbar Pin Will Force Q to Logic Low
D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs.
V_BB Output Reference Voltage
Pb-Free Packages are Available

User Guide

PURCHASE

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IMPORTANT NOTICE

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SHIPPING METHOD

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DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.