

INTEL EP1S60F1020C6
Manufacturer No:
EP1S60F1020C6
Manufacturer:
Package:
1020-BBGA
Description:
FPGAs Stratix® Series 1020-BBGA 1 mm mm
Quantity:
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EP1S60F1020C6 information
INTEL EP1S60F1020C6 technical specifications, attributes, parameters and parts with similar specifications to INTEL EP1S60F1020C6.
- Type
- Parameter
- Mounting Type
- Surface Mount
- Package / Case
- 1020-BBGA
- Surface Mount
- YES
- Supplier Device Package
- 1020-FBGA (33x33)
- Number of Terminals
- 1020
- Package Description
- 33 X 33 MM, 1 MM PITCH, FBGA-1020
- Package Style
- GRID ARRAY
- Moisture Sensitivity Level
- 3
- Package Body Material
- PLASTIC/EPOXY
- Package Equivalence Code
- BGA1020,31X31,50
- Supply Voltage-Nom
- 1.5 V
- Reflow Temperature-Max (s)
- 30
- Supply Voltage-Min
- 1.425 V
- Operating Temperature-Max
- 85 °C
- RoHS Status
- Non-RoHS Compliant
- Manufacturer Part Number
- EP1S60F1020C6
- Package Code
- BGA
- Package Shape
- SQUARE
- Manufacturer
- Altera Corporation
- Part Life Cycle Code
- Transferred
- Ihs Manufacturer
- ALTERA CORP
- Supply Voltage-Max
- 1.575 V
- Risk Rank
- 3.68
- Part Package Code
- BGA
- Series
- Stratix®
- JESD-609 Code
- e0
- Pbfree Code
- No
- Part Status
- Obsolete
- ECCN Code
- 3A001.A.7.A
- Terminal Finish
- Tin/Lead (Sn63Pb37)
- HTS Code
- 8542.39.00.01
- Subcategory
- Field Programmable Gate Arrays
- Technology
- CMOS
- Voltage - Supply
- 1.425 V ~ 1.575 V
- Terminal Position
- BOTTOM
- Terminal Form
- BALL
- Peak Reflow Temperature (Cel)
- 220
- Terminal Pitch
- 1 mm
- Reach Compliance Code
- not_compliant
- Base Part Number
- EP1S60
- Pin Count
- 1020
- JESD-30 Code
- S-PBGA-B1020
- Number of Outputs
- 1018
- Qualification Status
- Not Qualified
- Power Supplies
- 1.5,1.5/3.3 V
- Temperature Grade
- COMMERCIAL EXTENDED
- Number of I/O
- 773
Download datasheets and manufacturer documentation for INTEL EP1S60F1020C6.
EP1S60F1020C6 Overview
A 1020-BBGA package contains it, and it is available for download. There are FIELD PROGRAMMABLE GATE ARRAY transistors in this type of FPGA. Its 773 I/Os help it transfer data more efficiently. A fundamental building block contains 57120 logic elements or cells. An FPGA part from the Field Programmable Gate Arrays family. The Surface Mount-slot connector on the FPGA module can be connected to the development board. Fpga chips operates at a voltage of 1.425 V ~ 1.575 V and uses a battery to supply power. FPGAs belonging to the Stratix® series are a type of FPGA that belong to the Stratix® series of FPGAs. Operating temperatures should be maintained within the 0°C ~ 85°C (TJ) range at all times when the unit is in use. During the installation of this device, 1018 outputs were incorporated. Having a RAM bit size of 5215104 means that this device will offer you a lot of memory. For related parts, use its base part number EP1S60. 5712 LABs/CLBs are integrated into this FPGA. Power is supplied to the device by a 1.5,1.5/3.3 V battery. Featuring 1020 pins in total, it is a versatile device. In order to make the architecture work, 6570 CLBs are used. As most of the logic cells for the building blocks are 57120 logic cells, it incorporates a lot of logic. There is a device package provided by 1020-FBGA (33x33), which is the supplier. The configuration of the system is done using 1020 terminals.
EP1S60F1020C6 Features
773 I/Os
Up to 5215104 RAM bits
EP1S60F1020C6 Applications
There are a lot of ALTERA
EP1S60F1020C6 FPGAs applications.
- Integrating multiple SPLDs
- Voice recognition
- Cryptography
- Filtering and communication encoding
- Aerospace and Defense
- Medical Electronics
- Audio
- Automotive
- Consumer Electronics
- Distributed Monetary Systems
User Guide
Please verify all part numbers, quantities, and packaging preferences before placing your order. If substitutions are acceptable, please indicate this clearly. For time-sensitive projects, confirm estimated delivery dates and stock availability in advance. Once submitted, changes or cancellations may not be possible, especially for items marked as non-cancellable/non-returnable (NCNR). For international shipments, please ensure all import documentation is complete and accurate to avoid delays.
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