

INTEL EP1810LC-20
Manufacturer No:
EP1810LC-20
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Package:
Description:
FPGAs 1.27 mm mm
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EP1810LC-20 information
INTEL EP1810LC-20 technical specifications, attributes, parameters and parts with similar specifications to INTEL EP1810LC-20.
- Type
- Parameter
- Surface Mount
- YES
- Number of Terminals
- 68
- Package Description
- QCCJ, LDCC68,1.0SQ
- Package Style
- CHIP CARRIER
- Package Body Material
- PLASTIC/EPOXY
- Package Equivalence Code
- LDCC68,1.0SQ
- Supply Voltage-Nom
- 5 V
- Reflow Temperature-Max (s)
- NOT SPECIFIED
- Supply Voltage-Min
- 4.75 V
- Operating Temperature-Max
- 70 °C
- RoHS Status
- Non-RoHS Compliant
- Manufacturer Part Number
- EP1810LC-20
- Clock Frequency-Max
- 50 MHz
- Package Code
- QCCJ
- Package Shape
- SQUARE
- Manufacturer
- Altera Corporation
- Part Life Cycle Code
- Obsolete
- Number of I/O Lines
- 48
- Ihs Manufacturer
- ALTERA CORP
- Supply Voltage-Max
- 5.25 V
- Risk Rank
- 5.75
- Part Package Code
- LCC
- JESD-609 Code
- e0
- Pbfree Code
- No
- Terminal Finish
- Tin/Lead (Sn/Pb)
- Additional Feature
- MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
- HTS Code
- 8542.39.00.01
- Subcategory
- Programmable Logic Devices
- Technology
- CMOS
- Terminal Position
- QUAD
- Terminal Form
- J BEND
- Peak Reflow Temperature (Cel)
- NOT SPECIFIED
- Terminal Pitch
- 1.27 mm
- Reach Compliance Code
- compliant
- Pin Count
- 68
- JESD-30 Code
- S-PQCC-J68
- Qualification Status
- Not Qualified
- Power Supplies
- 5 V
- Temperature Grade
- COMMERCIAL
- Propagation Delay
- 22 ns
- Organization
- 12 DEDICATED INPUTS, 48 I/O
- Programmable Logic Type
- OT PLD
- Output Function
- MACROCELL
- Number of Macro Cells
- 48
- JTAG BST
- NO
- Number of Dedicated Inputs
- 12
- In-System Programmable
- NO
Download datasheets and manufacturer documentation for INTEL EP1810LC-20.
EP1810LC-20 Overview
In this kind of FPGA, OT PLD is used. The Programmable Logic Devices family of FPGAs includes this part. It is powered by a 5 V battery, which can be purchased separately. The device has a total of 68 pins on fpga semiconductor. As well as being characterized by a feature called MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS, it has another feature called A. To detect the status of input signals, there is a dedicated input which is used to detect the status of the input module. The main component of a CPLD is a set of 48 macrocells that form the foundation for the device. In order to configure it, it uses 68 terminals in total.
EP1810LC-20 Features
EP1810LC-20 Applications
There are a lot of ALTERA
EP1810LC-20 FPGAs applications.
- ASIC prototyping
- Medical imaging
- Computer hardware emulation
- Integrating multiple SPLDs
- Voice recognition
- Cryptography
- Filtering and communication encoding
- Aerospace and Defense
- Medical Electronics
- Audio
User Guide
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EP1810LC-20 Relevant information
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