Renesas DAC1653D1G5NLG-C1
Manufacturer No:
DAC1653D1G5NLG-C1
Manufacturer:
Renesas
Package:
Description:
High-Performance 16-Bit Dual DAC, Low Common Mode
Quantity:
In Stock :3800
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DAC1653D1G5NLG-C1 Information
Renesas DAC1653D1G5NLG-C1 technical specifications, attributes, parameters and parts with similar specifications to Renesas DAC1653D1G5NLG-C1.
- Type
- Parameter
- Pkg. Type
- VFQFPN
- Lead Count (#)
- 56
- Pb (Lead) Free
- Yes
- Carrier Type
- Tray
- Channels (#)
- 2
- Length (mm)
- 8
- MOQ
- 260
- Moisture Sensitivity Level (MSL)
- 3
- Package Area (mm²)
- 64.0
- Pb Free Category
- e3 Sn
- Type
- Parameter
- Pitch (mm)
- 0.5
- Pkg. Dimensions (mm)
- 8.0 x 8.0 x 0.85
- Power Consumption Typ (mW)
- 960
- Qty. per Carrier (#)
- 260
- Qty. per Reel (#)
- 0
- Requires Terms and Conditions
- Does not require acceptance of Terms and Conditions
- Resolution (bits)
- 16
- Supply Voltage (V)
- 1.2 - 1.2, 3.3 - 3.3
- Tape & Reel
- No
- Temp. Range
- -40 to +85°C
Download datasheets and manufacturer documentation for Renesas DAC1653D1G5NLG-C1.
The DAC1653D is a high-speed, high-performance 16-bit dual-channel digital-to-analog converter (DAC). The device provides sample rates up to 2.0Gsps with selectable 2x, 4x, and 8x interpolation filters optimized for multi-carrier and broadband wireless transmitters. The DAC165xD integrates a JEDEC JESD204B compliant high-speed serial input data interface running up to 10Gbps allowing dual-channel input sampling at up to 1Gsps over four differential lanes. It offers numerous advantages over traditional parallel digital interfaces.
- 1.0/1.5/2.0Gsps maximum output update rate
- 1Gsps maximum baseband input data rate
- 1, 2, or 4 configurable JESD204B serial input lanes running up to 10Gbps with embedded termination and programmable equalization
- JEDEC JESD204B device subclass I compliant: SYSREF-based deterministic and repeatable interface latency
- MDS enabling multiple DAC output streams being sample-level synchronized and phase coherent at the system-level
- Clock divider by 2,4,6,8 available at the input of the clock path with group delay compensation
- RF enable/disable pin and RF automatic mute for PA protection
- Power consumption 450mW per channel at 1.5Gsps
- Output common mode voltage 0.5V typical
- Typical dynamics performances: SFDR = 85dBc; IMD3= 85dBc; NSD = -164dBm/Hz
- Xilinx LogiCORE IP JESD204
- See: Altera JESD204B Reference Designs
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
