Texas Instruments CY74FCT652CTQCTG4

Manufacturer No:

CY74FCT652CTQCTG4

Manufacturer:

Texas Instruments

Package:

Description:

Octal Bus Transceivers and Registers with 3-State Outputs

Quantity:

In Stock :8836

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Expected Shipping：Sun, May 10 - Mon, May 11, 2026

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Date Code：Within 2 Years

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CY74FCT652CTQCTG4 Information

Texas Instruments CY74FCT652CTQCTG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments CY74FCT652CTQCTG4.

Type
Parameter

Supply voltage (min) (V)
4.75

Supply voltage (max) (V)
5.25

Number of channels
8

IOL (max) (mA)
64

IOH (max) (mA)
-32

Input type
TTL

Output type
TTL

Features
Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family
FCT

Rating
Catalog

Type
Parameter

Operating temperature range (°C)
-40 to 85

Package
SOIC (DW)

Pins
24

Size
159.65 mm² 15.5 x 10.3

Package
SSOP (DBQ)

Pins
24

Size
51.9 mm² 8.65 x 6

REACH Status
Yes

RoHS Status
RoHS Compliant

Download datasheets and manufacturer documentation for Texas Instruments CY74FCT652CTQCTG4.

The CY74FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA\ inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or stored-data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions of the appropriate clock (CPAB or CPBA) inputs, regardless of the select or enable levels of the control pins. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.