Renesas 9DBL0455NLGI8
Manufacturer No:
9DBL0455NLGI8
Manufacturer:
Renesas
Package:
Description:
VFQFPN 4.00X4.00X1.00 MM, 0.50MM.PCI Express (PCIe) Fanout Buffer (Distribution) IC 267MHz 1 Output 20-VFQFPN (4x4)
Quantity:
In Stock :6665
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
9DBL0455NLGI8 Information
Renesas 9DBL0455NLGI8 technical specifications, attributes, parameters and parts with similar specifications to Renesas 9DBL0455NLGI8.
- Type
- Parameter
- Lead Count (#)
- 20
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 1
- Qty. per Reel (#)
- 2500
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- -40 to 85°C
- Country of Assembly
- Taiwan
- Country of Wafer Fabrication
- Taiwan
- Type
- Parameter
- Price (USD)
- 2.22006
- Accepts Spread Spec Input
- Yes
- Advanced Features
- Flexible Power Sequencing, Power Down Tolerant, Loss of Signal Indicator
- App Jitter Compliance
- PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5
- Architecture
- Common, SRNS, SRIS
- Core Voltage (V)
- 3.3
- Diff. Input Signaling
- HCSL
- Diff. Inputs
- 1
- Diff. Output Signaling
- LP-HCSL
- Diff. Outputs
- 4
Download datasheets and manufacturer documentation for Renesas 9DBL0455NLGI8.
Datasheets:
The 9DBL0455 device is a 4-output PCIe clock fanout buffer for PCIe Gen 1–7 applications. It has an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock.
- Integrated terminations
- 85Ω transmission lines require 0 termination resistors
- 100Ω transmission lines require only 2 series resistors per output
- OE pin for each output supports CLKREQ# applications
- Intelligent power-down mode when all OE# pins are high (all outputs off)
- Spread-spectrum tolerant
- Open drain LOS# output indicates a loss of the input clock and returns the outputs to a Low/Low state
- Flexible power sequencing: Input clock is internally biased so a floating input clock will not inject noise into the system
- Power Down Tolerant: Control inputs will not clamp to ground or VDD if a signal is applied before chip VDD is applied
- Space saving 4mm × 4mm 20-VFQFPN
- Easy AC coupling to other logic families; see application note AN-891.
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12.28 M
Listed Part Number
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