Renesas 8V89316BAG8
Manufacturer No:
8V89316BAG8
Manufacturer:
Renesas
Package:
Description:
Ethernet PLL and IEEE 1588 Synthesizer
Quantity:
In Stock :3126
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Shipped from：HK Warehouse
Expected Shipping：Fri, May 29 - Sat, May 30, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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8V89316BAG8 Information
Renesas 8V89316BAG8 technical specifications, attributes, parameters and parts with similar specifications to Renesas 8V89316BAG8.
- Type
- Parameter
- Lead Count (#)
- 196
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 1000
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e1 SnAgCu
- Temp. Range
- 0 to 70°C
- Advanced Features
- Hitless Reference Switching, VCXO-based APLL
- App Jitter Compliance
- 1000BASE-X, 1000BASE-T, QSGMII
- Type
- Parameter
- Application
- System Synchronizer, IEEE 1588 Synthesizer
- Channels (#)
- 1
- Core Voltage (V)
- 3.3
- Diff. Inputs
- 1
- Diff. Outputs
- 6
- Input Freq (MHz)
- 25 - 156.25
- Input Freq Range Type
- Ethernet
- Input Type
- LVCMOS
- Inputs (#)
- 3
- Length (mm)
- 15
Download datasheets and manufacturer documentation for Renesas 8V89316BAG8.
The IDT8V89316 is used to frequency synchronize equipment with an Ethernet connected reference; its integrated DCO (Digitally Controlled Oscillator) can be controlled by an external IEEE 1588 clock recovery servo to synthesize IEEE 1588-based clocks. The IDT8V89316 low jitter output clocks can be used to directly time Gigabit Ethernet PHYs and QSGMII devices.
- Digital PLL synchronizes with Ethernet connected synchronization sources
- DPLL bandwidth is 1.2 Hz; DPLL holdover accuracy is 1.1X10-5 ppm
- Input references are monitored for frequency offset and activity
- DPLL holdover, free run and hitless reference switching can be forced by the host processor or can be automatically controlled by an internal state machine
- Internal DCO has resolution of 0.01105 ppb and can be controlled by an external processor via I2C interface for IEEE 1588 clock generation
- One Analog PLL for jitter attenuation
- Jitter generation <0.65ps RMS (10 kHz to 20 MHz), meets jitter requirements of 1 GbE PHYs and QSGMII
- IN1, IN2 and IN3 accept single ended reference clocks whose frequencies can be 25 MHz, 125 MHz or 156.25 MHz
- OUT1 outputs a differential clock with frequency of 125 MHz or 156.25 MHz
- OUT2 to OUT6 output differential clocks all with the same frequency of 125 MHz or 156.25 MHz
- OUT7 outputs a free-running LVCMOS clock with frequency of 25 MHz
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12.28 M
Listed Part Number
3,000+
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In-stock SKU
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