Renesas 8SLVD1212ANLGI/W
Manufacturer No:
8SLVD1212ANLGI/W
Manufacturer:
Renesas
Package:
Description:
1:12, LVDS Output Fanout Buffer
Quantity:
In Stock :9621
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Shipped from：HK Warehouse
Expected Shipping：Wed, Jun 3 - Thu, Jun 4, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
8SLVD1212ANLGI/W Information
Renesas 8SLVD1212ANLGI/W technical specifications, attributes, parameters and parts with similar specifications to Renesas 8SLVD1212ANLGI/W.
- Type
- Parameter
- Lead Count (#)
- 40
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 5000
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- -40 to +85°C
- Country of Assembly
- Taiwan
- Country of Wafer Fabrication
- Austria
- Type
- Parameter
- Additive Phase Jitter Typ RMS (fs)
- 65
- Additive Phase Jitter Typ RMS (ps)
- 0.065
- Adjustable Phase
- No
- Channels (#)
- 1
- Core Voltage (V)
- 2.5
- Family Name
- 8SLVD
- Function
- Buffer, Multiplexer
- Input Freq (MHz)
- 0 - 2000
- Input Type
- LVPECL, LVDS, CML
- Inputs (#)
- 2
Download datasheets and manufacturer documentation for Renesas 8SLVD1212ANLGI/W.
The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
- Twelve low skew, low additive jitter LVDS output pairs
- Two selectable, differential clock input pairs
- Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 2GHz (maximum)
- LVCMOS/LVTTL interface levels for the control input select pins
- Output skew: 40ps (max)
- Propagation delay: 310ps (typical)
- Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz to 20MHz: 77fs (typical) - Maximum device current consumption (IDD): 213mA
- 2.5V supply voltage
- Lead-free (RoHS 6), 40-lead VFQFN packaging
- -40 °C to 85 °C ambient operating temperature
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)