Renesas 8533AG-01LNT
Manufacturer No:
8533AG-01LNT
Manufacturer:
Renesas
Package:
Description:
Low Skew,1-to-4 Differential-to-3.3V LVPECL Fanout Buffer
Quantity:
In Stock :2365
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
8533AG-01LNT Information
Renesas 8533AG-01LNT technical specifications, attributes, parameters and parts with similar specifications to Renesas 8533AG-01LNT.
- Type
- Parameter
- Lead Count (#)
- 20
- Carrier Type
- Reel
- Moisture Sensitivity Level (MSL)
- 1
- Qty. per Reel (#)
- 3000
- Qty. per Carrier (#)
- 0
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- 0 to 70°C
- Additive Phase Jitter Typ RMS (fs)
- 60
- Additive Phase Jitter Typ RMS (ps)
- 0.06
- Type
- Parameter
- Core Voltage (V)
- 3.3
- Function
- Buffer, Multiplexer
- Input Freq (MHz)
- 0 - 650
- Input Type
- CML, HCSL, HSTL, LVDS, LVPECL, SSTL
- Inputs (#)
- 2
- Length (mm)
- 6.5
- MOQ
- 3000
- Output Banks (#)
- 1
- Output Freq Range (MHz)
- 0 - 650
- Output Skew (ps)
- 30
Download datasheets and manufacturer documentation for Renesas 8533AG-01LNT.
The 8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The 8533- 01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8533-01 ideal for those applications demanding well defined performance and repeatability.
- Four differential 3.3V LVPECL outputs
- Selectable differential CLK, nCLK or LVPECL clock inputs
- CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
- Maximum output frequency: 650MHz
- Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
- Output skew: 30ps (maximum)
- Part-to-part skew: 150ps (maximum)
- Propagation delay: 1.4ns (maximum)
- Additive phase jitter, RMS: 0.06ps (typical)
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Lead-Free packages available
- Industrial temperature information available upon request
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
