Microchip ZL30735BLDG1

The ZL30735B is a network synchronization chip with up to eight independent DPLLs, five extremely low output jitter synthesizers plus extraordinary features to ease customers’ design and increase the flexibility.

Having new features, such as fast boot, partial reset, per-input DPLL settings, cascading DPLL and NCO holdover, combined with industry leading IEEE1588 Precision Time Protocol and Synchronization algorithm, makes the solution ideal for applications such as routers, switches, optical transparent network and 4G/5G wireless base stations (CU/DU/RU).

We also have ZL3064x as line card jitter attenuators, such as ZL30642B, to form full SyncE&IEEE1588 Timing solution for any rack system.

Click here to know about our full IEEE1588 software solution and profiles we can support.

Highlights
• Combined with IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithm software modules
• Ultra Precise Timing for 5G Radio Access Networks
• Five independent DPLL clock channels plus three additional DPLLs for NCO Hybrid, Split XO and redundant oscillator modes
• Inputs: up to 10, differential or single-ended
• Hitless reference switching
• Per-input DPLL settings to allow input switching smoothly
• Any-to-any frequency conversion per channel
• Cascade DPLL to support one DPLL sourced from the other
• Five output synthesizers
• Outputs: up to 10 differential, up to 20 CMOS
• Output jitter 100 fs RMS typical for 156.25 MHz 12 kHz to 20 MHz
• Core power consumption <0.9W

Packet and/or physical-layer frequency, phase and time synchronization
• Physical-layer compliance with ITU-T G.8262, G.8262.1, G.813, G.812, Telcordia GR-1244, GR-253
• Packet-timing compliance with ITU-T G.8261, G.8263, G.8273.2 (class A,B,C,D), G.8273.4
• Enables 5G wireless applications with sub-100 ns time/phase alignment requirements

General Features
• Automatic self-configuration at power-up from internal Flash memory, 7 configurations
• MiToDSync 1-wire time-of-day interface in/out
• MiToDBasic 3-wire time-of-day interface out
• Reset-to-clocks <20 ms for all Synth0 outputs
• Partial reset to keep all Synth0 outputs toggling
• Input-to-output alignment <100 ps
• Numerically controlled oscillator behavior in each DPLL and each synthesizer
• NCO holdover support
• Holdover time counter
• Easy-to-configure design requires no external VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
• SPI or I2C processor Interface
• 1.8V and 3.3V core VDD voltages