ZL30672LFG7-Microchip-Price, Stock & Datasheet

The ZL30672 offers 2 channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.

AN3467 Crystals and Oscillators for Next Generation Timing Solutions

ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices

ZLAN-656 Redwood PSNR

ZLAN-664 Board Design Recommendations for Redwood

ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood

ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package

ZLAN-724 Phase Measurement Compensation for Redwood

ZLAN-728 Indirect Read and Write Procedure

Two independent clock channels

Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure

Ultra-fast lock to GPS/GNSS and 1PPS for faster power-up time for 4G LTE, 5G & Wireless Infrastructure

Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems

Split oscillator option lowers cost, lowers jitter, and provides redundancy

Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3

Excellent jitter performance of 240 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs

Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz

One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz

8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs

Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths

Up to three programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz

Accepts up to 10 differential or 10 single ended input references

Full reference monitoring of electrical failures

Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb

Any input reference can be fed with clock, sync (frame pulse), clock /sync pair

Easy Configuration and dynamic programming via SPI/I2C interface

Factory programming available

Operates from a single crystal resonator or clock oscillator

Microchip ZL30672LFG7

Manufacturer No:

ZL30672LFG7

Manufacturer:

Microchip

Package:

Description:

Synchronous Ethernet Dual Channel Packet Clock Network Synchronizer

In Stock :1273

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ISO 9001:2015

ANSI/ESD S20.20

ZL30672LFG7 Information

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ZL30672LFG7 Relevant information

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