Microchip ZL30274LDG1

Manufacturer No:

ZL30274LDG1

Manufacturer:

Microchip

Package:

Description:

2-Channel Jitter Attenuator with up to 20 Outputs

Quantity:

In Stock :5535

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Shipped from：HK Warehouse

Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026

Lead Time：Inquire about availability

Date Code：Within 2 Years

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DELIVERY TIME

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2. For in-stock parts, orders normally could be shipped out within 1-2days.

ZL30274LDG1 Information

Microchip ZL30274LDG1 technical specifications, attributes, parameters and parts with similar specifications to Microchip ZL30274LDG1.

Type
Parameter

Type
Ultra-Low Jitter

Inputs
4 D/8SE

CMOS Outputs
20

Low-Jitter Synthesizers
2

Typical Jitter (12kHz-20MHz) fs RMS
100

Diff InputFreq. Range
1 kHz to 1250 MHz

Output Freq Range
0.5 Hz to 750 MHz

Type
Parameter

Download datasheets and manufacturer documentation for Microchip ZL30274LDG1.

Product Brief:

80df34e25ae6adf469f338e9ffc3b704.pdf

The ZL30274 is a feature-rich jitter attenuator with DPLLs and five extremely low output jitter synthesizers. This device is ideal for frequency conversion, jitter attenuation and frequency synthesis in a wide variety of equipment types requiring low jitter (<150fs) and multiple frequency families

Other devices in this family include ZL30731, ZL30732, ZL30733, ZL30734, ZL30631, ZL30632, ZL30633, ZL30634, ZL30635, ZL30641, ZL30642, ZL30643, ZL30644, ZL30645 and ZL30640 which are targeted for 5G SyncE and IEEE1588 timing card and line card applications.

Any-to-any frequency conversion per channel
Inputs: up to 6, differential or singled-ended
Outputs: up to 10 differential, up to 20 CMOS
Output jitter <150fs RMS 156.25MHz 12k-20M
Core power consumption <0.9W

Any input frequency from 1kHz to 1250MHz
Per-input activity and frequency monitoring
Automatic or manual reference switching
Revertive or nonrevertive switching
Any input can be a 0.5Hz to 8kHz Sync input for Ref+Sync frequency/phase/time locking
Input phase measurement, 1ps resolution
Per-input phase adjustment, 1ps resolution DPLLs

Hitless reference switching
Per-DPLL phase adjustment, 1ps resolution
Programmable bandwidth, tracking range, phase-slope limiting and other advanced features
Locking to gapped-clock input signals

Any frequency 0.5Hz to 750MHz
Each OUTP/N pair can be LVDS, LVPECL, 2xCMOS, Low-Vcm or programmable differential
In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
VDD per output pair, CMOS voltages 1.8V-3.3V
Per-synth phase adjustment, 1ps resolution
Per-output duty cycle adjustment
Precise output alignment circuitry and peroutput phase adjustment
Per-output enable/disable and glitchless start/stop (stop high or low)

Operates from a single oscillator 9.72-400MHz

Automatic self-configuration at power-up from internal Flash memory, 7 configurations
Input-to-output alignment <100ps
Numerically controlled oscillator behavior in each DPLL and each synthesizer
Easy-to-configure design requires no external VCXO or loop filter components
5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
SPI or I2C processor Interface
1.8V and 3.3V core VDD voltages
Easy-to-use evaluation/programming software