

Microchip ZL30112LDG1
Manufacturer No:
ZL30112LDG1
Manufacturer:
Package:
32-VFQFN Exposed Pad
Description:
SLIC/CODEC PLL
Quantity:
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In Stock :Available
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ZL30112LDG1 information
Microchip ZL30112LDG1 technical specifications, attributes, parameters and parts with similar specifications to Microchip ZL30112LDG1.
- Type
- Parameter
- Type
- General Purpose
- Inputs
- 1
- CMOS Outputs
- 2
- Low-Jitter Synthesizers
- 0
- Typical Jitter (12kHz-20MHz) fs RMS
- \u003c600
- Diff InputFreq. Range
- 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
- Output Freq Range
- 8.192 MHz
Download datasheets and manufacturer documentation for Microchip ZL30112LDG1.
Data Sheets:
The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.
The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.
- Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
- Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse
- Automatic entry and exit from freerun mode on reference fail
- Provides DPLL lock and reference fail indication
- DPLL bandwidth of 29 Hz for all rates of input references
- Less than 0.6 nsecpp intrinsic jitter on all output clocks
- 20 MHz external master clock source: clock oscillator or crystal
- Simple hardware control interface
User Guide
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
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