Microchip ZL30110LDG1
Microchip ZL30110LDG1

Microchip ZL30110LDG1

Manufacturer No:

ZL30110LDG1

Manufacturer:

Microchip

Package:

32-VFQFN Exposed Pad

Description:

Telecom Rate Conversion DPLL

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Step1：Prepare product

Step1：Prepare product

Step2：Desiccant Protection

Step2：Desiccant Protection

Step3：Vacuum Packaging

Step3：Vacuum Packaging

Step4：Individual Package

Step4：Individual Package

Step5：Anti-collision Filling

Step5：Anti-collision Filling

Step6：Packaging Box

Step6：Packaging Box

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DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

ZL30110LDG1 Information

Microchip ZL30110LDG1 technical specifications, attributes, parameters and parts with similar specifications to Microchip ZL30110LDG1.

  • Type
  • Parameter
  • Type
  • General Purpose
  • Inputs
  • 1
  • CMOS Outputs
  • 9
  • Low-Jitter Synthesizers
  • 0
  • Typical Jitter (12kHz-20MHz) fs RMS
  • \u003c5000
  • Diff InputFreq. Range
  • 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
  • Output Freq Range
  • 65.536 MHz
  • Type
  • Parameter

Download datasheets and manufacturer documentation for Microchip ZL30110LDG1.

Data Sheets:

The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.

  • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
  • Provides DPLL lock and reference fail indication
  • Automatic free run mode on reference fail
  • DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
  • Less than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs
  • Minimal input to output and output to output skew
  • 25 MHz external master clock source: clock oscillator or crystal
  • Simple hardware control interface
      • Provides a range of output clocks:
    • 65.536 MHz TDM clock locked to the input reference
    • General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
    • General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator

    ZL30110LDG1 Relevant information

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