Microchip ZL30105QDG1

Manufacturer No:

ZL30105QDG1

Manufacturer:

Microchip

Package:

64-TQFP

Description:

Stratum 3 Redundant System Clock Synchronizer for T1/E1/SDH, Advanced TCA and H.110

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In Stock :Available

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ZL30105QDG1 information

Microchip ZL30105QDG1 technical specifications, attributes, parameters and parts with similar specifications to Microchip ZL30105QDG1.

Type
Parameter

Type
General Purpose

Inputs
3

CMOS Outputs
11

Low-Jitter Synthesizers
0

Typical Jitter (12kHz-20MHz) fs RMS
Up to OC-3/STM-1

Diff InputFreq. Range
2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

Output Freq Range
65.536 MHz

Download datasheets and manufacturer documentation for Microchip ZL30105QDG1.

Data Sheets:

908f07a5d9b184f034af5df725389202.pdf

The ZL30105 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 3 and SDH timing specifications. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter.
The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications.

Accepts three input references and synchronizes to any combination of 2, 8 kHz, 1.544, 2.048, 8.192, 16.384 or 19.44 MHz inputs
Synchronizes to clock-and-sync-pair to maintain minimal phase skew between redundant system clocks
Provides a range of clock outputs: 1.544, 2.048, 3.088, 16.384, and 19.44 MHz, and either 4.096 and 8.192 MHz or 32.768 and 65.536 MHz, and a choice of 6.312, 8.448, 44.736 or 34.368 MHz
Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
Ultra-low jitter of less than 20 psRMS on the 19.44 MHz clock
Less than 600 psp-p intrinsic jitter on all the other clock and frame pulse outputs
Holdover frequency accuracy of 1x10-8
Simple hardware control interface offers manual or automatic hitless reference switching
Supports ITU-T G.813 option 1, G.823 for 2048 kbs and G.824 for 1544 kbs interfaces
Supports Telcordia GR-1244-CORE Stratum 3/4/4E
Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces

User Guide

PURCHASE

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IMPORTANT NOTICE

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SHIPPING COST

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SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.