Microchip SY58051AUMG-TR

Manufacturer No:

SY58051AUMG-TR

Manufacturer:

Microchip

Package:

16-VFQFN Exposed Pad

Description:

Ultra-Precision CML AnyGate,,with Internal Input and Output Termination

Quantity:

Delivery:

Payment:

In Stock :Available

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SY58051AUMG-TR information

Microchip SY58051AUMG-TR technical specifications, attributes, parameters and parts with similar specifications to Microchip SY58051AUMG-TR.

Type
Parameter

Description
CML Universal Gate with Internal Input and Output Termination

Input
CML, PECL

Supply Voltage
2.5/3.3

Max Freq (GHz)
2

Icc (mA)
250

Max Within Device Skew (ps)
25

OE
False

Input Mux
False

Number Of Outputs
0

Max Prop Delay (ps)
160

Download datasheets and manufacturer documentation for Microchip SY58051AUMG-TR.

Data Sheets:

59208c22b7552461157f246d1d6bf084.pdf

The SY58051AU is an ultra-fast, low jitter universal logic gate with a guaranteed maximum data or clock throughput of 10.7Gbps or 8GHz, respectively. This AnyGate® differential logic device will produce many logic functions of two Boolean variables, such as AND, NAND, OR, NOR, DELAY, or NEGATION.The SY58051AU differential inputs include a unique internal termination design that allows access to the termination network throughout a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled, without external resistor-bias and termination networks. The result is a clean, stub-free, low-jitter interface solution. The differential CML output is optimized for environments with internal 50Ω source termination and a 400mV output swing.The SY58051AU operates from a 2.5V or 3.3V supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY58051AU is part of Micrel’s Precision Edge® product family.

Three matched-delay input pair provide any logic function: AND, NAND, OR, NOR
DC to >10.7Gbps data rate throughput
DC to >8GHz clock fMAX
<160ps Any In-to-Out tpd
20ps typical tr / tf
0.2psRMS typical random jitter (data)
2psPP typical deterministic jitter (data)
5psPP typical total jitter (clock)
46fsRMS typical additive phase jitter (clock)
Unique input termination and VT pin accepts AC- coupled and DC-coupled inputs (CML, PECL)
Internal 50O output source termination
Typical 400mV CML output swing (RL = 50O)
Internal 50O input termination
Power supply 2.5V ±5% or 3.3V ±10%
-40°C to +85°C industrial temperature range
Available in a 16-pin (3mm x 3mm) QFN package

User Guide

PURCHASE

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