Microchip SY100EL15LZG
Microchip SY100EL15LZG

Microchip SY100EL15LZG

Manufacturer No:

SY100EL15LZG

Manufacturer:

Microchip

Package:

16-SOIC (0.154, 3.90mm Width)

Description:

3.3V 1:4 Clock Distribution

Delivery:

DHL
DHL
DHL
DHL

Payment:

DHL
DHL
DHL
DHL
DHL
DHL
DHL

In Stock :Available

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SY100EL15LZG information

Microchip SY100EL15LZG technical specifications, attributes, parameters and parts with similar specifications to Microchip SY100EL15LZG.

  • Type
  • Parameter
  • Description
  • 2:4
  • Input
  • PECL
  • Output
  • PECL
  • Supply Voltage
  • 3.3
  • Max Freq (GHz)
  • 0.75
  • Icc (mA)
  • 25
  • Max Within Device Skew (ps)
  • 50
  • OE
  • True
  • Input Mux
  • True
  • Number Of Outputs
  • 0
  • Buffer Type
  • Fanout
  • Fanout
  • 1:4
  • Max Prop Delay (ps)
  • 750

Download datasheets and manufacturer documentation for Microchip SY100EL15LZG.

Application Notes:

Data Sheets:

The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.

The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input.The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control.The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2.

    • 3.3V power supply
    • 50ps output-to-output skew
    • Low power
    • Synchronous enable/disable
    • Multiplexed clock input
    • 75KO internal input pull-down resistors
    • Available in 16-pin SOIC package

User Guide

PURCHASE

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IMPORTANT NOTICE

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Step1：Prepare product

Step2：Desiccant Protection

Step2：Desiccant Protection

Step3：Vacuum Packaging

Step3：Vacuum Packaging

Step4：Individual Package

Step4：Individual Package

Step5：Anti-collision Filling

Step5：Anti-collision Filling

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Step6：Packaging Box

SHIPPING COST

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2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.

SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

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