Renesas SSTE32882KB1AKG
Manufacturer No:
SSTE32882KB1AKG
Manufacturer:
Renesas
Package:
Description:
CABGA-176(8x13.5) Application Specific Clock/Timing ROHS
Quantity:
In Stock :3019
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Shipped from：HK Warehouse
Expected Shipping：Sat, May 30 - Sun, May 31, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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SHIPPING COST
1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
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3. It may cost additional remote fees for delivery if you are in a remote area.
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
SSTE32882KB1AKG Information
Renesas SSTE32882KB1AKG technical specifications, attributes, parameters and parts with similar specifications to Renesas SSTE32882KB1AKG.
- Type
- Parameter
- Pkg. Type
- CABGA
- Lead Count (#)
- 176
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 0
- Qty. per Carrier (#)
- 170
- Pb (Lead) Free
- Yes
- Pb Free Category
- e1 SnAgCu
- Temp. Range
- 0 to 70°C
- Function
- Register + PLL (Low Power)
- Type
- Parameter
- Length (mm)
- 13.5
- MOQ
- 340
- Package Area (mm²)
- 108.0
- Pitch (mm)
- 0.65
- Pkg. Dimensions (mm)
- 13.5 x 8.0 x 1.1
- Published
- No
- Requires Terms and Conditions
- Does not require acceptance of Terms and Conditions
- SDRAM Type
- DDR3-800 to 2133
- Supply Voltage (V)
- 1.25 - 1.25, 1.35 - 1.35, 1.5 - 1.5
- Tape & Reel
- No
Download datasheets and manufacturer documentation for Renesas SSTE32882KB1AKG.
Datasheet:
This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation
- DDR3-800/1066/1333/1600/1866/2133 rate
- 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
- Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
- Supports LVCMOS switching levels on the RESET and MIRROR inputs
- Checks priority on DIMM-independent data inputs
- Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
- Supports CKE Power Down operation modes
- Supports Quad Chip Select operation features
- RESET input disables differential input receivers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
- Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications
- Latch-up performance exceeds 100mA
- ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
