STMicroelectronics SPC584B70E5CD00X
Manufacturer No:
SPC584B70E5CD00X
Manufacturer:
STMicroelectronics
Package:
Description:
32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family
Quantity:
In Stock :4835
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
SPC584B70E5CD00X Information
STMicroelectronics SPC584B70E5CD00X technical specifications, attributes, parameters and parts with similar specifications to STMicroelectronics SPC584B70E5CD00X.
- Type
- Parameter
- Supply Voltage Min Volt
- 3.0
- Supply Voltage Max Volt
- 5.5
- Operating Temp Min Celsius
- -40.0
- Operating Temp Max Celsius
- 105.0
- Core
- e200z4d
- ECCN US
- 5A991.b.4.a
- ECCN EU
- NEC
- Packing Type
- Tape And Reel
- RoHS Status
- Grade
- Automotive Safety
- Type
- Parameter
- Package Name
- TQFP 144 20x20x1.0
- Supply Voltage Min Volt
- 3.0
- Supply Voltage Max Volt
- 5.5
- Operating Temp Min Celsius
- -40.0
- Operating Temp Max Celsius
- 105.0
- Core
- e200z4d
- ECCN US
- 5A991.b.4.a
- ECCN EU
- NEC
- Packing Type
- Tape And Reel
- RoHS Status
Download datasheets and manufacturer documentation for STMicroelectronics SPC584B70E5CD00X.
Data sheet:
Material Declaration:
- AEC-Q100 qualified
- High performance e200z420
- 32-bit Power Architecture technology CPU
- Core frequency as high as 120 MHz
- Variable Length Encoding (VLE)
- 2112 KB (2048 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
- 176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
- 128 KB on-chip general-purpose SRAM (in addition to 64 KB core local data RAM
- Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
- Multi-channel direct memory access controller (eDMA) with 64 channels
- 1 interrupt controller (INTC)
- Comprehensive new generation ASIL-B safety concept
- ASIL-B of ISO 26262
- FCCU for collection and reaction to failure notifications
- Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
- Cyclic redundancy check (CRC) unit
- Enhanced low power support
- Ultra low power STANDBY
- Smart Wake-up Unit
- Fast wake-up and execute from RAM
- Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution
- Body cross triggering unit (BCTU)
- Triggers ADC conversions from any eMIOS channel
- Triggers ADC conversions from up to 2 dedicated PIT_RTIs
- Enhanced analog-to-digital converter system with:
- 2 independent fast 12-bit SAR analog converters
- 1 supervisor 12-bit SAR analog converter
- 1 10-bit SAR analog converter with STDBY mode support
- Communication interfaces
- 1 Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
- 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support
- 14 LINFlexD modules
- 7 Deserial Serial Peripheral Interface (DSPI) modules
- Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
- Nexus Development Interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard
- Boot Assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART
- Junction temperature range -40 °C to 150 °C
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12.28 M
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