Texas Instruments SN74LVTH573PWRG4
Manufacturer No:
SN74LVTH573PWRG4
Manufacturer:
Package:
Description:
3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs
Quantity:
In Stock :9960
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SN74LVTH573PWRG4 Information
Texas Instruments SN74LVTH573PWRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74LVTH573PWRG4.
- Type
- Parameter
- Number of channels
- 8
- Technology family
- LVT
- Supply voltage (min) (V)
- 2.7
- Supply voltage (max) (V)
- 3.6
- Input type
- TTL-Compatible CMOS
- Output type
- 3-State
- Clock frequency (max) (MHz)
- 160
- IOL (max) (mA)
- 64
- IOH (max) (mA)
- -32
- Supply current (max) (µA)
- 5000
- Type
- Parameter
- Features
- Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)
- Operating temperature range (°C)
- -40 to 85
- Rating
- Catalog
- Package
- SOIC (DW)
- Pins
- 20
- Size
- 131.84 mm² 12.8 x 10.3
- Package
- SOP (NS)
- Pins
- 20
- Size
- 98.28 mm² 12.6 x 7.8
- Package
- SSOP (DB)
Download datasheets and manufacturer documentation for Texas Instruments SN74LVTH573PWRG4.
User guide:
Data sheet:
Application note:
Selection guide:
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Ioff and Power-Up 3-State Support Hot Insertion
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74LVTH573PWRG4 Relevant information
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