Texas Instruments SN74LVTH273DBRG4
Manufacturer No:
SN74LVTH273DBRG4
Manufacturer:
Package:
Description:
3.3-V ABT Octal D-Type Flip-Flops With Clear
Quantity:
In Stock :2884
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SN74LVTH273DBRG4 Information
Texas Instruments SN74LVTH273DBRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74LVTH273DBRG4.
- Type
- Parameter
- Number of channels
- 8
- Technology family
- LVT
- Supply voltage (min) (V)
- 2.7
- Supply voltage (max) (V)
- 3.6
- Input type
- TTL-Compatible CMOS
- Output type
- Push-Pull
- Clock frequency (max) (MHz)
- 150
- IOL (max) (mA)
- 64
- IOH (max) (mA)
- -32
- Supply current (max) (µA)
- 5000
- Type
- Parameter
- Features
- Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)
- Operating temperature range (°C)
- -40 to 85
- Rating
- Catalog
- Package
- SOIC (DW)
- Pins
- 20
- Size
- 131.84 mm² 12.8 x 10.3
- Package
- SOP (NS)
- Pins
- 20
- Size
- 98.28 mm² 12.6 x 7.8
- Package
- SSOP (DB)
Download datasheets and manufacturer documentation for Texas Instruments SN74LVTH273DBRG4.
Selection guide:
User guide:
Data sheet:
Application note:
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Support Unregulated Battery Operation Down to 2.7 V
- Buffered Clock and Direct-Clear Inputs
- Individual Data Input to Each Flip-Flop
- Ioff Supports Partial-Power-Down-Mode Operation
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74LVTH273DBRG4 Relevant information
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