TI SN74LS76ADR

Manufacturer No:

SN74LS76ADR

Manufacturer:

Package:

16-SOIC (0.154, 3.90mm Width)

Description:

4.75V~5.25V 45MHz JK Type Flip Flop DUAL 74LS76 74LS Series 16-SOIC (0.154, 3.90mm Width)

Quantity:

In Stock :9119

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Shipping & Availability

Fast worldwide shipping via DHL, FedEx, UPS, and EMS.

Shipped from：HK Warehouse

Expected Shipping：Thu, May 7 - Fri, May 8, 2026

Lead Time：Inquire about availability

Date Code：Within 2 Years

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User Guide

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PURCHASE

Please verify all part numbers, quantities, and packaging preferences before placing your order. If substitutions are acceptable, please indicate this clearly. For time-sensitive projects, confirm estimated delivery dates and stock availability in advance. Once submitted, changes or cancellations may not be possible, especially for items marked as non-cancellable/non-returnable (NCNR). For international shipments, please ensure all import documentation is complete and accurate to avoid delays.

MEANS OF PAYMENT

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RFQ (REQUEST FOR QUOTATIONS)

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Provide target prices and acceptable alternatives, if any, to speed up the quotation process.

IMPORTANT NOTICE

Quotations are subject to stock availability and may vary with market conditions. Prices and lead times are not guaranteed until a purchase order is confirmed. Ensure your contact details are correct to avoid delays in response.

Step1：Prepare product

Step2：Desiccant Protection

Step3：Vacuum Packaging

Step4：Individual Package

Step5：Anti-collision Filling

Step6：Packaging Box

SHIPPING COST

1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.

SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

SN74LS76ADR Information

TI SN74LS76ADR technical specifications, attributes, parameters and parts with similar specifications to TI SN74LS76ADR.

Type
Parameter

Mount
Surface Mount

Mounting Type
Surface Mount

Package / Case
16-SOIC (0.154, 3.90mm Width)

Operating Temperature
0°C~70°C TA

Packaging
Tape & Reel (TR)

Series
74LS

Pbfree Code
no

Part Status
Obsolete

Moisture Sensitivity Level (MSL)
1 (Unlimited)

Number of Terminations
16

Type
Parameter

Type
JK Type

Additional Feature
MASTER SLAVE OPERATION

Subcategory
FF/Latches

Technology
TTL

Voltage - Supply
4.75V~5.25V

Terminal Position
DUAL

Terminal Form
GULL WING

Peak Reflow Temperature (Cel)
NOT SPECIFIED

Supply Voltage
5V

Reach Compliance Code
not_compliant

Download datasheets and manufacturer documentation for TI SN74LS76ADR.

SN74LS76ADR Overview

The flip flop is packaged in 16-SOIC (0.154, 3.90mm Width). Package Tape & Reel (TR)embeds it. As configured, the output uses Differential. In the configuration of the trigger, Negative Edgeis used. There is an electrical part that is mounted in the way of Surface Mount. With a supply voltage of 4.75V~5.25V volts, it operates. It is operating at 0°C~70°C TA. Logic flip flops of this type are classified as JK Type. FPGAs belonging to the 74LSseries contain this type of chip. It should not exceed 45MHzin its output frequency. In total, there are 2 elements. Currently, there are 16 terminations. The 74LS76family includes it. The D flip flop is powered by a voltage of 5V . Devices in the LSfamily are electronic devices. A part of the electronic system is mounted in the way of Surface Mount. This device has Positive Edgeas its clock edge trigger type. There is a base part number FF/Latchesfor the RS flip flops. A normal operating voltage (Vsup) should remain above 4.75V. It runs on 5Vvolts of power. In terms of quiescent current, it consumes 4mA . Additionally, you may refer to the D latch's additional MASTER SLAVE OPERATION.