Texas Instruments SN74ALVCH374PWRG4

Manufacturer No:

SN74ALVCH374PWRG4

Manufacturer:

Texas Instruments

Package:

Description:

Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State Outputs

Quantity:

In Stock :7957

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Date Code：Within 2 Years

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SN74ALVCH374PWRG4 Information

Texas Instruments SN74ALVCH374PWRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74ALVCH374PWRG4.

Type
Parameter

Number of channels
8

Technology family
ALVC

Supply voltage (min) (V)
1.65

Supply voltage (max) (V)
3.6

Input type
Standard CMOS

Output type
3-State

Clock frequency (max) (MHz)
150

IOL (max) (mA)
24

IOH (max) (mA)
-24

Supply current (max) (µA)
10

Type
Parameter

Features
Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)
-40 to 85

Rating
Catalog

Package
SOIC (DW)

Pins
20

Size
131.84 mm² 12.8 x 10.3

Package
TSSOP (PW)

Pins
20

Size
41.6 mm² 6.5 x 6.4

Package
TVSOP (DGV)

Download datasheets and manufacturer documentation for Texas Instruments SN74ALVCH374PWRG4.

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Operates From 1.65 V to 3.6 V
Max t_pd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)