Texas Instruments SN74ABT646ADBRG4

Manufacturer No:

SN74ABT646ADBRG4

Manufacturer:

Texas Instruments

Package:

Description:

Octal Bus Transceivers And Registers With 3-State Outputs

Quantity:

In Stock :4359

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Date Code：Within 2 Years

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SN74ABT646ADBRG4 Information

Texas Instruments SN74ABT646ADBRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74ABT646ADBRG4.

Type
Parameter

Supply voltage (min) (V)
4.5

Supply voltage (max) (V)
5.5

Number of channels
8

IOL (max) (mA)
64

IOH (max) (mA)
-32

Input type
TTL

Output type
TTL

Features
Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family
ABT

Rating
Catalog

Type
Parameter

Operating temperature range (°C)
-40 to 85

Package
SOIC (DW)

Pins
24

Size
159.65 mm² 15.5 x 10.3

Package
SOP (NS)

Pins
24

Size
117 mm² 15 x 7.8

Package
SSOP (DB)

Pins
24

Size
63.96 mm² 8.2 x 7.8

Download datasheets and manufacturer documentation for Texas Instruments SN74ABT646ADBRG4.

These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’ABT646A devices.

Output-enable (OE\) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Typical V_OLP (Output Ground Bounce)
<1 V at V_CC = 5 V, T_A = 25°C
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)