

Texas Instruments SN65LVDS18DRFTG4
Manufacturer No:
SN65LVDS18DRFTG4
Manufacturer:
Texas Instruments
Package:
Description:
2.5-V/3.3-V oscillator gain stage/buffer with enable
Quantity:


In Stock :8731
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SN65LVDS18DRFTG4 Information
Texas Instruments SN65LVDS18DRFTG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN65LVDS18DRFTG4.
- Type
- Parameter
- Function
- Buffer, Translator
- Protocols
- LVDS, LVPECL
- Number of transmitters
- 1
- Number of receivers
- 1
- Supply voltage (V)
- 2.5, 3.3
- Signaling rate (Mbps)
- 2000
- Input signal
- Single-ended
- Output signal
- LVDS
- Rating
- Catalog
- Operating temperature range (°C)
- -40 to 85
- Type
- Parameter
- Package
- WSON (DRF)
- Pins
- 8
- Size
- 4 mm² 2 x 2
- REACH Status
- Yes
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Texas Instruments SN65LVDS18DRFTG4.
Data sheet:
EVM User's guide:
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
- Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
- Clock Rates to 1 GHz
- 250-ps Output Transition Times
- 0.12 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
- 2.5-V or 3.3-V Supply Operation
- 2-mm x 2-mm Small-Outline No-Lead Package
- APPLICATIONS
- PECL-to-LVDS Translation
- Clock Signal Amplification
SN65LVDS18DRFTG4 Relevant information
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