Renesas RC32012A000GN2#BB0
Manufacturer No:
RC32012A000GN2#BB0
Manufacturer:
Renesas
Package:
Description:
IC CLOCK GENERATOR 72VFQFPN.Clock Generator, Jitter Attenuator IC 250MHz 1 72-VFQFN Exposed Pad
Quantity:
In Stock :9620
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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RC32012A000GN2#BB0 Information
Renesas RC32012A000GN2#BB0 technical specifications, attributes, parameters and parts with similar specifications to Renesas RC32012A000GN2#BB0.
- Type
- Parameter
- Lead Count (#)
- 72
- Carrier Type
- Tray
- Moisture Sensitivity Level (MSL)
- 3
- Qty. per Reel (#)
- 0
- Qty. per Carrier (#)
- 168
- Pb (Lead) Free
- Yes
- Pb Free Category
- e3 Sn
- Temp. Range
- -40 to +85°C
- 105°C Max. Case Temp.
- 0
- Adjustable Phase
- Yes
- Type
- Parameter
- Advanced Features
- PWM Encoder/Decoder, ToD, 1PPS, DCO, IEEE 1588, JESD204B, JESD204C, T-BC, T-TSC Class C, eEEC
- Application
- Wireless Baseband Unit (BBU), Distributed Unit (DU), Centralized Unit (CU), Radio Unit (RU)
- Channels (#)
- 6
- Core Voltage (V)
- 2.5, 3.3
- DPLL Channels (#)
- 6
- Diff. Inputs
- 5
- Diff. Outputs
- 12
- Family Name
- ClockMatrix
- Feedback Divider Resolution (bits)
- 48
- Fractional Output Dividers (#)
- 6
Download datasheets and manufacturer documentation for Renesas RC32012A000GN2#BB0.
Datasheet:
The RC32012A regenerates and distributes ultra-low jitter clock outputs and features up to four independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for IEEE 1588 clock synthesis, SyncE clock generation, jitter attenuation, and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 56Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The RC32012A is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards, and wireless small cell applications.
- Two timing channels and four independent frequency domains
- Output jitter below 100fs RMS
- Digital PLLs (DPLLs) lock to any frequency from 0.5kHz to 1GHz
- DPLLs/Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
- DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
- Can be used as a jitter attenuator, clock generator, or synchronizer
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring, and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive/non-revertive and other programmable settings
- Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
- The device can configure itself automatically after reset via:
- Internal Customer-programmable One-Time Programmable memory
- Standard external I²C EPROM via separate I²C Master Port
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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