Renesas R1QDA4418RBG-19IA0
Manufacturer No:
R1QDA4418RBG-19IA0
Manufacturer:
Renesas
Package:
Description:
144-Mbit QDR™II+ SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT
Quantity:
In Stock :7893
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.
Currently, our products are shipped through DHL, FedEx, SF, and UPS.
DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
R1QDA4418RBG-19IA0 Information
Renesas R1QDA4418RBG-19IA0 technical specifications, attributes, parameters and parts with similar specifications to Renesas R1QDA4418RBG-19IA0.
- Type
- Parameter
- Pkg. Type
- LBGA
- Carrier Type
- Tray
- Architecture
- QDR-II+ with ODT
- Burst Length (Words)
- 4
- Data Width (bits)
- 18000
- Density (Kb)
- 144000
- Frequency (Max) (MHz)
- 533
- Lead Compliant
- No
- Lead Count (#)
- 165
- Length (mm)
- 17
- Type
- Parameter
- MIN Frequency (MHz)
- 250
- MOQ
- 1
- Pb (Lead) Free
- No
- Pkg. Dimensions (mm)
- 17 x 15 x 1.4
- Read Latency (Clock)
- 2.5
- Tape & Reel
- No
- Thickness (mm)
- 1.4
- Width (mm)
- 15
- RoHS Status
- RoHS Compliant
- Pb (Lead) Free
- No
Download datasheets and manufacturer documentation for Renesas R1QDA4418RBG-19IA0.
The R1QDA4436RBG is a 4, 194, 304-word by 36-bit and the R1QDA4418RBG is a 8, 388, 608-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
- Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
- Clock Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with μs restart
- I/O Separate independent read and write data ports with concurrent transactions 100% bus utilization DDR read and write operation HSTL I/O User programmable output impedance PLL circuitry for wide output data valid window and future frequency scaling Data valid pin (QVLD) to indicate valid data on the output
- Function Four-tick burst for reduced address frequency Internally self-timed write control Simple control logic for easy depth expansion JTAG 1149.1 compatible test access port
- Package 165 FBGA package (15 x 17 x 1.4 mm)
AIChipLink – Your Trusted Electronic Components Distributor
12.28 M
Listed Part Number
3,000+
Leading Manufacturers
4.9 M
In-stock SKU
15,000+
Warehouse Area(㎡)
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