Renesas R1Q3A7218ABB-33IB0
Manufacturer No:
R1Q3A7218ABB-33IB0
Manufacturer:
Renesas
Package:
Description:
72-Mbit QDR™II SRAM 4-word Burst
Quantity:
In Stock :4397
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Shipped from：HK Warehouse
Expected Shipping：Sun, May 31 - Mon, Jun 1, 2026
Lead Time：Inquire about availability
Date Code：Within 2 Years
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
R1Q3A7218ABB-33IB0 Information
Renesas R1Q3A7218ABB-33IB0 technical specifications, attributes, parameters and parts with similar specifications to Renesas R1Q3A7218ABB-33IB0.
- Type
- Parameter
- Pkg. Type
- LBGA
- Carrier Type
- Tray
- Architecture
- QDR-II
- Burst Length (Words)
- 4
- Data Width (bits)
- 18000
- Density (Kb)
- 72000
- Frequency (Max) (MHz)
- 300
- Lead Compliant
- Yes
- Lead Count (#)
- 165
- Length (mm)
- 15
- Type
- Parameter
- MIN Frequency (MHz)
- 180
- MOQ
- 1
- Moisture Sensitivity Level (MSL)
- 3
- Pb (Lead) Free
- Yes
- Pkg. Dimensions (mm)
- 15 x 13 x 1.4
- Read Latency (Clock)
- 1.5
- Tape & Reel
- No
- Thickness (mm)
- 1.4
- Width (mm)
- 13
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Renesas R1Q3A7218ABB-33IB0.
The R1Q3A7236 is a 2, 097, 152-word by 36-bit and the R1Q3A7218 is a 4, 194, 304-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
- Power Supply · 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
- Clock · Fast clock cycle time for high bandwidth · Two input clocks (K and /K) for precise DDR timing at clock rising edges only · Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches · Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems · Clock-stop capability with μs restart
- I/O · Separate independent read and write data ports with concurrent transactions · 100% bus utilization DDR read and write operation · HSTL I/O · User programmable output impedance · DLL/PLL circuitry for wide output data valid window and future frequency scaling
- Function · Four-tick burst for reduced address frequency · Internally self-timed write control · Simple control logic for easy depth expansion · JTAG 1149.1 compatible test access port
- Package · 165 FBGA package (13 x 15 x 1.4 mm) · RoHS Compliance Level = 6/6
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12.28 M
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