NXP P2020NXE2MHC
Manufacturer No:
P2020NXE2MHC
Manufacturer:
Package:
689-BBGA Exposed Pad
Description:
1mm PowerPC e500v2 1.05V 32-bit Microprocessor QorIQ P2 Series P2020 1.05V 689-BBGA Exposed Pad
Quantity:
In Stock :Available
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Step1：Prepare product
Step2：Desiccant Protection
Step3：Vacuum Packaging
Step4：Individual Package
Step5：Anti-collision Filling
Step6：Packaging Box
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DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
P2020NXE2MHC Information
NXP P2020NXE2MHC technical specifications, attributes, parameters and parts with similar specifications to NXP P2020NXE2MHC.
- Type
- Parameter
- Factory Lead Time
- 12 Weeks
- Package / Case
- 689-BBGA Exposed Pad
- Surface Mount
- YES
- Operating Temperature
- -40°C~125°C TA
- Packaging
- Tray
- Series
- QorIQ P2
- Published
- 2002
- JESD-609 Code
- e2
- Part Status
- Active
- Moisture Sensitivity Level (MSL)
- 3 (168 Hours)
- Type
- Parameter
- Number of Terminations
- 689
- ECCN Code
- 5A002.A.1
- Terminal Finish
- TIN COPPER/TIN SILVER
- HTS Code
- 8542.31.00.01
- Subcategory
- Microprocessors
- Technology
- CMOS
- Terminal Position
- BOTTOM
- Terminal Form
- BALL
- Peak Reflow Temperature (Cel)
- 260
- Supply Voltage
- 1.05V
Download datasheets and manufacturer documentation for NXP P2020NXE2MHC.
Datasheets:
Environmental Information:
PCN Packaging:
P2020NXE2MHC Description
A link status bit (TBI SR [Link Status]) in the TBI Status Register (SR) represents the current state of the SGMII link. The TBI link status bit should become a b'1 after detecting IDLE sequences if Auto-Negotiation (AN) is disabled, and stay at b'1 as long as valid data is received and the TBI is not reset. After numerous invalid characters are received or the TBI is reset, the TBI link status bit should become a b'0, indicating the link is down. When AN is enabled, the TBI link status bit is not set to b'1 until auto-negotiation is complete (TBI CR [AN DONE]=1), but the same criteria apply as when AN is disabled for the TBI link status bit to be set to b'1.
P2020NXE2MHC Features
? PIC (programmable interrupt controller) that adheres to the OpenPIC standard
? Two DMA controllers with four channels
? Timers, DUART, and two I2C controllers
? A more powerful local bus controller (TBC)
? 16 I/O signals for generic use
? Temperature of the operating junction
? WB-TePBGA II, 689-pin, 31 x 31 mm (wire bond temperature-enhanced plastic BGA)
P2020NXE2MHC Relevant information
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