
ONSEMI NB6L295MNG
Manufacturer No:
NB6L295MNG
Manufacturer:
Package:
24-VFQFN Exposed Pad
Description:
Dual Channel Programmable Delay Line with LVPECL Output
Quantity:
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NB6L295MNG information
ONSEMI NB6L295MNG technical specifications, attributes, parameters and parts with similar specifications to ONSEMI NB6L295MNG.
- Type
- Parameter
- Case Outline
- 485L-01
- MSL Type
- 1
- Input Level
- CML
- Output Level
- ECL
- fMax Typ (MHz)
- 1500
- td(prog) Max (ns)
- 6.9
- tR & tF Max (ps)
- 170
- MSL Temp (°C)
- 260
- Container Type
- TUBE
- Container Qty.
- 92
- td(step) Typ (ps)
- 8.7
- tJitter Typ (ps)
- 3
- Package Type
- QFN-24
- VCC Typ (V)
- 3.3
- td(prog) Min (ns)
- 0
Download datasheets and manufacturer documentation for ONSEMI NB6L295MNG.
Datasheet:
Package Drawing:
The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de-skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of two operating modes, a Dual Delay or an Extended Delay. In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel. The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore, the Extended Delay path starts at the IN0/IN0 inputs, flows through PD0, cascades to the PD1 and outputs through Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended Delay Mode. The required delay is accomplished by programming each delay channel via a 3-pin Serial Data Interface, described in the application section. The digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode. The Multi-Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single-ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24-pin QFN Pb-free package. The NB6L295 is a member of the ECLinPS MAX family of high performance products.
Application
- Automated Test Equipment (ATE)Adjustable signal path delays
Feature
- Linearity +/- 20ps Maximum
- Maximum Input Clock Frequency >1.5 GHz Typical
- Programmable Range: 0 ns to 6 ns Dual Mode; Programmable Range: 0 ns to 11
- 11 ps Delay Increments
- INx/INxb Inputs Accept LVPECL, LVDS Levels
- 3-Wire Serial Data Interface (SDI)
User Guide
Please verify all part numbers, quantities, and packaging preferences before placing your order. If substitutions are acceptable, please indicate this clearly. For time-sensitive projects, confirm estimated delivery dates and stock availability in advance. Once submitted, changes or cancellations may not be possible, especially for items marked as non-cancellable/non-returnable (NCNR). For international shipments, please ensure all import documentation is complete and accurate to avoid delays.
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