NXP MPC561MZP56
Manufacturer No:
MPC561MZP56
Manufacturer:
Package:
388-BBGA
Description:
ROMless PowerPC 32-Bit Microcontroller MPC5xx Series MPC561 2.6V 388-BBGA
Quantity:
User Guide
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Step1：Prepare product
Step2：Desiccant Protection
Step3：Vacuum Packaging
Step4：Individual Package
Step5：Anti-collision Filling
Step6：Packaging Box
1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.
Currently, our products are shipped through DHL, FedEx, SF, and UPS.
DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
MPC561MZP56 Information
NXP MPC561MZP56 technical specifications, attributes, parameters and parts with similar specifications to NXP MPC561MZP56.
- Type
- Parameter
- Factory Lead Time
- 14 Weeks
- Mounting Type
- Surface Mount
- Package / Case
- 388-BBGA
- Surface Mount
- YES
- Operating Temperature
- -40°C~125°C TA
- Packaging
- Tray
- Series
- MPC5xx
- Published
- 1998
- JESD-609 Code
- e0
- Part Status
- Not For New Designs
- Type
- Parameter
- Moisture Sensitivity Level (MSL)
- 3 (168 Hours)
- Number of Terminations
- 388
- ECCN Code
- 3A991.A.2
- Terminal Finish
- Tin/Lead/Silver (Sn/Pb/Ag)
- HTS Code
- 8542.31.00.01
- Subcategory
- Microcontrollers
- Technology
- CMOS
- Terminal Position
- BOTTOM
- Terminal Form
- BALL
- Peak Reflow Temperature (Cel)
- 240
Download datasheets and manufacturer documentation for NXP MPC561MZP56.
Environmental Information:
MPC561MZP56 Features
High-performance microprocessor
? Single clock-cycle execution for many instructions
Five independent execution units and two register files
? Independent LSU for load and store operations
? BPU featuring static branch prediction
? A 32-bit integer unit (IU)
? 32 general-purpose registers (GPRs) for integer operands
? 32 floating-point registers (FPRs) for single- or double-precision operands
Facilities for enhanced system performance
? Atomic memory references
In-system testability and debugging features
High instruction and data throughput
? Condition register (CR) look-ahead operations performed by BPU
? Branch-folding capability during execution (zero-cycle branch execution time)
? Programmable static branch prediction on unresolved conditional branches
? A pre-fetch queue that can hold up to four instructions, providing the look-ahead capability
? Interlocked pipelines with feed-forwarding that control data dependencies in hardware
Class code compression model support
? Efficient use of internal Flash (MPC564) and external Flash (MPC562/MPC564) by increasing
code density up to 100%
MPC561MZP56 Relevant information
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