Microchip MD1210K6-G

Manufacturer No:

MD1210K6-G

Manufacturer:

Microchip

Package:

12-VQFN Exposed Pad

Description:

MOSFET, HIGH SPEED, DUAL DRIVER

Quantity:

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In Stock :Available

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MD1210K6-G information

Microchip MD1210K6-G technical specifications, attributes, parameters and parts with similar specifications to Microchip MD1210K6-G.

Type
Parameter

# of Channels
2

Input Voltage min (V)
1.2

Input Voltage max (V)
5

Output Voltage Bipolar (V)
--

Output Voltage Unipolar (V)
0 - 12

Package
QFN-12

Download datasheets and manufacturer documentation for Microchip MD1210K6-G.

Application Notes:

b7b75ddb50accfb4b7ec559166f38d0e.pdf

Data Sheets:

f368746aa18d7b04e273719a4c2b1cc6.pdf

MD1210 is a high speed, dual MOSFET driver. It is designed to drive high voltage P and N-channel MOSFET transistors for medical ultrasound and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1210 can operate from 1.2V to 5.0V logic interface with an optimum operating input signal range of 1.8V to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. VDD1, VDD2, and VH should be connected to the positive supply voltage, and VSS1, VSS2, and VL should be connected to 0V or to Ground. The GND pin is the logic control input signal digital ground. The output stage is capable of peak currents of up to ±2.0A, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A output high and the B output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.

6ns rise and fall time with 1000pF load
2.0A peak output source/sink current
1.2V to 5.0V input CMOS compatible
4.5V to 13V single positive supply voltage
Smartlogic threshold
Low jitter design
Two matched channels
Outputs can swing below ground
Low inductance package
Thermally-enhanced package

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