Microchip MCP37D21-200E/TE
Manufacturer No:
MCP37D21-200E/TE
Manufacturer:
Microchip
Package:
121-TFBGA
Description:
14-bit 200 Msps Pipelined ADC
Quantity:
In Stock :7510
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Expected Shipping：Thu, May 28 - Fri, May 29, 2026
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Date Code：Within 2 Years
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MCP37D21-200E/TE Information
Microchip MCP37D21-200E/TE technical specifications, attributes, parameters and parts with similar specifications to Microchip MCP37D21-200E/TE.
- Type
- Parameter
- Resolution
- 14
- Sample Rate kSPS Max
- 200000
- Input Channels Differential
- 8
- SNRtyp
- 74.2
- SFDR typ
- 90
- ENOB
- 12
- INL Typ LSB
- 0.5
- Type
- Parameter
Download datasheets and manufacturer documentation for Microchip MCP37D21-200E/TE.
Application Notes:
Data Sheets:
User Guide:
The MCP37D21-200 is a 14-bit pipelined A/D converter with a maximum sampling rate of 200 Msps. The high accuracy of over 74 dB Signal-to-Noise Ratio (SNR) and over 90 dB Spurious Free Dynamic Range (SFDR) enable high precision measurements of fast input signals. The device operates at very low power consumption of 490 mW at 200 Msps including LVDS digital I/O. Lower power saving modes are available at 144 mW for Standby and 28 mW for Shutdown. The MCP37D21-200 includes many digital processing features that simplify system design, cost and power usage. These include an integrated digital down-converter with onboard NCO, decimation filters for improved SNR, individual phase, offset and gain adjustment and a fractional delay recovery for time-delay corrections in multi-channel modes. Data is available through the serial DDR LVDS or parallel CMOS interface and configured via SPI. The device is available in the TFBGA-121 and VTLA-124 packages. TFBGA-121 package is qualified for automotive applications (AEC-Q100).
- 14-bit resolution
- 200 Msps maximum sampling rate
- Low power 490 mW operation at full sampling rate, including LVDS digital I/O
- Power saving modes of 144 mW during Standby and 28 mW during Shutdown
- >74 dBFS SNR at 200 Msps
- >90 dBFS SFDR at 200 Msps
- Integrated digital down-converter
- Decimation filters for improved SNR
- Phase, offset and gain adjustment of individual channels
- Fractional delay recovery for time-delay corrections in multi-channel operations (dual/octal-channel modes)
- Input channel bandwidth of 500 MHz
- Output data format in serial DDR LVDS or parallel CMOS
- Configuration via Serial Peripheral Interface (SPI)
- TFBGA-121 Package: AEC-Q100 qualified, Temperature Grade 1: -40°C to +125°C
- VTLA-124 Package: Temperature Range: -40°C to +85°C
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