NXP MC9S12XEQ512MAG

MC9S12XEQ512MAG  Description

The MC9S12XE-Family of microcontrollers is a further development of the S12XD-Family including new features for enhanced system integrity and greater functionality. These new features include a Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with enhanced EEPROM functionality (EEE), an enhanced XGATE, and an Internally filtered, frequency modulated Phase Locked Loop (IPLL), and an enhanced ATD. The E-Family extends the S12X product range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship MC9S12XE100.

The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU. It retains the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of

compatibility between the S12XE and S12XD families.

MC9S12XEQ512MAG  Features

16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high-priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H, and P configurable as rising or falling edge sensitive interrupts

EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M, and up to 4MByte address spaces

— Each chip select output can be configured to complete the transaction on either the time-out of one

of the two wait state generators or the deassertion of the EWAIT signal

MMC (module mapping control)

DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

BDM (background debug mode)

MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8 bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation