NXP MC9S12XA512CAG
Manufacturer No:
MC9S12XA512CAG
Manufacturer:
Package:
144-LQFP
Description:
512KB 512K x 8 FLASH 16-Bit Microcontroller HCS12X Series 9S12XA512 2.5V 144-LQFP
Quantity:
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MC9S12XA512CAG Information
NXP MC9S12XA512CAG technical specifications, attributes, parameters and parts with similar specifications to NXP MC9S12XA512CAG.
- Type
- Parameter
- Factory Lead Time
- 10 Weeks
- Mounting Type
- Surface Mount
- Package / Case
- 144-LQFP
- Surface Mount
- YES
- Operating Temperature
- -40°C~85°C TA
- Packaging
- Tray
- Series
- HCS12X
- Published
- 2005
- JESD-609 Code
- e3
- Part Status
- Active
- Type
- Parameter
- Moisture Sensitivity Level (MSL)
- 3 (168 Hours)
- Number of Terminations
- 144
- ECCN Code
- 3A991.A.2
- Terminal Finish
- Matte Tin (Sn)
- Additional Feature
- IT ALSO REQUIRES 5 V SUPPLY
- HTS Code
- 8542.31.00.01
- Subcategory
- Microcontrollers
- Technology
- CMOS
- Terminal Position
- QUAD
- Terminal Form
- GULL WING
Download datasheets and manufacturer documentation for NXP MC9S12XA512CAG.
Datasheets:
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PCN Design/Specification:
PCN Packaging:
MC9S12XA512CAG Description
The MC9S12XD family will retain the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family. Based on an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12. The MC9S12XD family introduces the performance-boosting XGATE module. Using enhanced DMA functionality, this parallel processing module offloads the CPU by providing high-speed data processing and transfer between peripheral modules, RAM, Flash EEPROM, and I/O ports. Providing up to 80 MIPS of performance added to the CPU, the XGATE can access all peripherals, Flash EEPROM, and the RAM block.
MC9S12XA512CAG Features
HCS12X Core
— 16-bit HCS12X CPU
– Upward compatible with MC9S12 instruction set
– Interrupt stacking and programmer’s model identical to MC9S12
– Instruction queue
– Enhanced indexed addressing
– Enhanced instruction set
— EBI (external bus interface)
— MMC (module mapping control)
— INT (interrupt controller)
— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
— BDM (background debug mode)
XGATE (peripheral coprocessor)
— Parallel processing module offloads the CPU by providing high-speed data processing and
transfer
— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
PIT (periodic interrupt timer)
— Four timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
CRG (clock and reset generator)
— Low noise/low power Pierce oscillator
— PLL
— COP watchdog
— Real-time interrupt
— Clock monitor
— Fast wake-up from stop mode
Port H & Port J with interrupt functionality
— Digital filtering
— Programmable rising or falling edge trigger
Memory
— 512, 256, and 128-Kbyte Flash EEPROM
— 4 and 2-Kbyte EEPROM
— 32, 16, and 12-Kbyte RAM
One 16-channel and one 8-channel ADC (analog-to-digital converter)
MC9S12XA512CAG Relevant information
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