ONSEMI MC100LVEL34DR2G

Manufacturer No:

MC100LVEL34DR2G

Manufacturer:

ONSEMI

Package:

16-SOIC (0.154, 3.90mm Width)

Description:

3.3 V ECL ÷·2, ÷·4, ÷·8 Divider

Quantity:

In Stock :5329

Looking for price or availability? Send us an RFQ and our sales team will respond quickly.

Shipping & Availability

Fast worldwide shipping via DHL, FedEx, UPS, and EMS.

Shipped from：HK Warehouse

Expected Shipping：Mon, May 11 - Tue, May 12, 2026

Lead Time：Inquire about availability

Date Code：Within 2 Years

Payment

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All components supplied by Aichiplink are sourced from trusted global suppliers and verified through strict in-house inspection and quality control procedures.

Quality Assurance

Certified in-house inspection and testing facilities ensure all components meet internationally recognized quality standards.

User Guide

Aichiplink operates certified in-house inspection and testing facilities to ensure all electronic components meet internationally recognized quality and compliance standards. Our quality management system is verified through ISO 9001 certification and industry-standard inspection procedures.

PURCHASE

Please verify all part numbers, quantities, and packaging preferences before placing your order. If substitutions are acceptable, please indicate this clearly. For time-sensitive projects, confirm estimated delivery dates and stock availability in advance. Once submitted, changes or cancellations may not be possible, especially for items marked as non-cancellable/non-returnable (NCNR). For international shipments, please ensure all import documentation is complete and accurate to avoid delays.

MEANS OF PAYMENT

For your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and Wire Transfer. Net terms may be available for qualified customers upon approval.

RFQ (REQUEST FOR QUOTATIONS)

Please ensure the part numbers and quantities are accurate and complete when submitting your RFQ.
Provide target prices and acceptable alternatives, if any, to speed up the quotation process.

IMPORTANT NOTICE

Quotations are subject to stock availability and may vary with market conditions. Prices and lead times are not guaranteed until a purchase order is confirmed. Ensure your contact details are correct to avoid delays in response.

Step1：Prepare product

Step2：Desiccant Protection

Step3：Vacuum Packaging

Step4：Individual Package

Step5：Anti-collision Filling

Step6：Packaging Box

SHIPPING COST

1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.

SHIPPING METHOD

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.

MC100LVEL34DR2G Information

ONSEMI MC100LVEL34DR2G technical specifications, attributes, parameters and parts with similar specifications to ONSEMI MC100LVEL34DR2G.

Type
Parameter

VCC Typ (V)
3.3

fMax Typ (MHz)
1500

tpd Typ (ns)
0.7

Case Outline
751B-05

Type
Divider

Input Level
ECL

Output Level
ECL

Container Qty.
2500

tR & tF Max (ps)
400

Package Type
SOIC-16

Type
Parameter

MSL Type
1

MSL Temp (°C)
260

Container Type
REEL

Download datasheets and manufacturer documentation for ONSEMI MC100LVEL34DR2G.

Datasheet:

12a592da24f2cfb3dddcd902dac93658.pdf

Package Drawing:

cfcc683b473d074f91911bcaac8bf397.pdf

7b54d75480e7d0546e020f19b82af689.pdf

The MC100LVEL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable (EN bar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulsecould lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon start−up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internaldividers, as well as multiple LVEL34s in a system.