
ONSEMI MC100EPT21DTG
Manufacturer No:
MC100EPT21DTG
Manufacturer:
Package:
8-TSSOP, 8-MSOP (0.118, 3.00mm Width)
Description:
Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator
Quantity:
Delivery:




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In Stock :Available
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MC100EPT21DTG information
ONSEMI MC100EPT21DTG technical specifications, attributes, parameters and parts with similar specifications to ONSEMI MC100EPT21DTG.
- Type
- Parameter
- Output Level
- TTL
- tpd Typ (ns)
- 1.4
- tR & tF Max (ps)
- 900
- Case Outline
- 948R-02
- MSL Type
- 3
- MSL Temp (°C)
- 260
- Container Type
- TUBE
- Container Qty.
- 100
- Package Type
- TSSOP-8
- Channels
- 1
- Input Level
- CML
- VCC Typ (V)
- 3.3
- fMax Typ (MHz)
- 350
Download datasheets and manufacturer documentation for ONSEMI MC100EPT21DTG.
Datasheet:
The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBB output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single-ended direct connection.
Application
- Precision Clock Translation
Feature
- 1.4ns Typical Propagation Delay
- Maximum Frequency > 275 MHz Typical
- 24mA TTL outputs
- LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
- The 100 Series Contains Temperature Compensation
- VBB Output
- New Differential Input Common Mode Range
User Guide
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