
ONSEMI MC100EP35DTG
Manufacturer No:
MC100EP35DTG
Manufacturer:
Package:
8-TSSOP, 8-MSOP (0.118, 3.00mm Width)
Description:
ECL JK Flip-Flop
Quantity:


In Stock :5891
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User Guide
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Quotations are subject to stock availability and may vary with market conditions. Prices and lead times are not guaranteed until a purchase order is confirmed. Ensure your contact details are correct to avoid delays in response.

Step1:Prepare product

Step2:Desiccant Protection

Step3:Vacuum Packaging

Step4:Individual Package

Step5:Anti-collision Filling

Step6:Packaging Box
1. Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.).
2. Some specific products need to reach the minimum order quantity.
3. It may cost additional remote fees for delivery if you are in a remote area.
Currently, our products are shipped through DHL, FedEx, SF, and UPS.
DELIVERY TIME1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.
MC100EP35DTG Information
ONSEMI MC100EP35DTG technical specifications, attributes, parameters and parts with similar specifications to ONSEMI MC100EP35DTG.
- Type
- Parameter
- Bits
- 1
- VCC Typ (V)
- 5
- Container Qty.
- 100
- tsu Min (ns)
- 0.15
- tR & tF Max (ps)
- 170
- fToggle Typ (MHz)
- 3000
- Type
- JK-Type
- Input Level
- CML
- Output Level
- ECL
- tJitter Typ (ps)
- 0.2
- Type
- Parameter
- th Min (ns)
- 0.15
- trec Typ (ns)
- 0.15
- Package Type
- TSSOP-8
- Case Outline
- 948R-02
- MSL Type
- 3
- MSL Temp (°C)
- 260
- Container Type
- TUBE
- tpd Typ (ns)
- 0.41
Download datasheets and manufacturer documentation for ONSEMI MC100EP35DTG.
Datasheet:
Package Drawing:
The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.The 100 Series contains temperature compensation.
Application
- Using ECL Logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies.
End Product
- Telecommunications Equipment
Feature
- 410 ps Propagation Delay
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
- Open Input Default State
- Q Output will default LOW with inputs open or at VEE
- Pb-Free Packages are Available
MC100EP35DTG Relevant information
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