ONSEMI MC100EP195BMNG
Manufacturer No:
MC100EP195BMNG
Manufacturer:
Package:
32-VFQFN Exposed Pad
Description:
3.3 V ECL Programmable Delay Chip
Quantity:
In Stock :Available
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MC100EP195BMNG Information
ONSEMI MC100EP195BMNG technical specifications, attributes, parameters and parts with similar specifications to ONSEMI MC100EP195BMNG.
- Type
- Parameter
- MSL Temp (°C)
- 260
- td(prog) Max (ns)
- 12.11
- tJitter Typ (ps)
- 2.6
- Package Type
- QFN-32
- VCC Typ (V)
- 3.3
- td(prog) Min (ns)
- 8.95
- td(step) Typ (ps)
- 11
- Case Outline
- 488AM
- Output Level
- ECL
- fMax Typ (MHz)
- 1200
- Type
- Parameter
- tR & tF Max (ps)
- 300
- Input Level
- CML
- Container Type
- TUBE
- Container Qty.
- 74
- MSL Type
- 2
Download datasheets and manufacturer documentation for ONSEMI MC100EP195BMNG.
Datasheet:
Package Drawing:
The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(9:0) values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D(9:0). A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D(10:0). The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3.
Application
- Automated Test Equipment (ATE)
Feature
- Maximum Input Clock Frequency >1.2 GHz Typical
- Programmable Range: 0 ns to 10 ns
- Delay Range: 2.2 ns to 12.2 ns
- 10 ps Increments
- PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V
- NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V
- IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels
- A Logic High on the EN Pin Will Force Q to Logic Low
- D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels
- VBB Output Reference Voltage
MC100EP195BMNG Relevant information
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