ONSEMI M74VHC1GT126DF2G
Manufacturer No:
M74VHC1GT126DF2G
Manufacturer:
Package:
5-TSSOP, SC-70-5, SOT-353
Description:
Single Non-Inverting Buffer, TTL Level
Quantity:
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M74VHC1GT126DF2G Information
ONSEMI M74VHC1GT126DF2G technical specifications, attributes, parameters and parts with similar specifications to ONSEMI M74VHC1GT126DF2G.
- Type
- Parameter
- Case Outline
- 419A-02
- MSL Temp (°C)
- 260
- Container Type
- REEL
- Container Qty.
- 3000
- Channels
- 1
- Output
- 3-State
- VCC Min (V)
- 2
- Package Type
- SC-88A / SC-70-5
- VCC Max (V)
- 5.5
- tpd Max (ns)
- 7.5
- Type
- Parameter
- IO Max (mA)
- 8
- MSL Type
- 1
Download datasheets and manufacturer documentation for ONSEMI M74VHC1GT126DF2G.
Datasheet:
The MC74VHC1GT126 is a single gate noninverting 3-state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC1GT126 requires the 3-state control input (OE(bar)) to be set Low to place the output into the high impedance state. The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high-voltage power supply. The MC74VHC1GT126 input structure provides protection when voltages up to 5.5V are applied, regardless of the supply voltage. This allows the MC74VHC1GT126 to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.
Application
- This product is general usage and suitable for many different applications.
End Product
- *Standard Device (No Specific End Product)
Feature
- Designed for 2.0 V to 5.5 V VCC Operation
- High Speed: tPD = 3.5ns (Typ) at V CC = 5V
- Low Power Dissipation: ICC = 1µA (Max) at TA = 25°C
- TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V
- CMOS-Compatible Outputs: VOH > 0.8VCC ; VOL < 0.1VCC @Load
- Power Down Protection Provided on Inputs and Outputs
- Balanced Propagation Delays
- Pin and Function Compatible with Other Standard Logic Families
- Chip Complexity: FETs = ≤ 100
- Pb-Free Packages are Available
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