Texas Instruments LMX1404MPAPTEP
Manufacturer No:
LMX1404MPAPTEP
Manufacturer:
Texas Instruments
Package:
Description:
15 GHz Buffer/Multiplier/Divider with SYSREF (JESD204B/C support) and FPGA Clock
Quantity:
In Stock :1951
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Expected Shipping：Fri, May 29 - Sat, May 30, 2026
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Date Code：Within 2 Years
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LMX1404MPAPTEP Information
Texas Instruments LMX1404MPAPTEP technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments LMX1404MPAPTEP.
- Type
- Parameter
- Integrated VCO
- No
- Frequency (min) (MHz)
- 300
- Frequency (max) (MHz)
- 12800
- Current consumption (mA)
- 405
- Features
- Enhanced Product, Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Ultra-low additive jitter
- Rating
- HiRel Enhanced Product
- Operating temperature range (°C)
- -55 to 125
- Lock time (µs) (typ) (s)
- Loop BW dependent
- Package
- HTQFP (PAP)
- Pins
- 64
- Type
- Parameter
- Size
- 144 mm² 12 x 12
- REACH Status
- Yes
- RoHS Status
- RoHS Compliant
Download datasheets and manufacturer documentation for Texas Instruments LMX1404MPAPTEP.
Data sheet:
Application note:
Certificate:
The LMX1404-EP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.
- VID #V62/24627
- Clock buffer for 300MHz to 15GHz frequency
- Ultra-Low Noise
- Noise floor of –159dBc/Hz at 6GHz output
- 36-fs additive jitter (100Hz to fCLK) at 6GHz output
- 5fs additive jitter (100Hz - 100MHz)
- 4 high-frequency clocks with corresponding SYSREF outputs
- Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and 8
- Shared programmable multiplier x2, x3, and x4
- Support pin mode options to configure the device without SPI
- LOGICLK output with corresponding SYSREF output
- On separate divide bank
- 1, 2, 4 pre-divider
- 1 (bypass), 2, …, 1023 post divider
- 8 programmable output power levels
- Synchronized SYSREF clock outputs
- 508 delay step adjustments of less than 2.5ps each at 12.8GHz
- Generator and repeater modes
- Windowing feature for SYSREFREQ pins to optimize timing
- SYNC feature to all divides and multiple devices
- 2.5V operating voltage
- –55ºC to 125ºC operating temperature
- High Reliability
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Extended Product Life Cycle
- Product Traceability
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12.28 M
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