

LATTICE LC5512MV-45FN256C
Manufacturer No:
LC5512MV-45FN256C
Manufacturer:
Package:
LEAD FREE, FPBGA-256
Description:
EE PLD, 5.7ns, 512-Cell, CMOS, PBGA256, LEAD FREE, FPBGA-256
Quantity:
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LC5512MV-45FN256C information
LATTICE LC5512MV-45FN256C technical specifications, attributes, parameters and parts with similar specifications to LATTICE LC5512MV-45FN256C.
- Type
- Parameter
- Pbfree Code
- Yes
- RoHS Status
- RoHS Compliant
- Part Life Cycle Code
- Obsolete
- Ihs Manufacturer
- LATTICE SEMICONDUCTOR CORP
- Part Package Code
- BGA
- Package Description
- LEAD FREE, FPBGA-256
- Pin Count
- 256
- Reach Compliance Code
- compliant
- ECCN Code
- EAR99
- HTS Code
- 8542.39.00.01
- Additional Feature
- YES
- In-System Programmable
- YES
- JESD-30 Code
- S-PBGA-B256
- JESD-609 Code
- e1
- JTAG BST
- YES
- Length
- 17 mm
- Moisture Sensitivity Level
- 3
- Number of I/O Lines
- 193
- Number of Macro Cells
- 512
- Number of Terminals
- 256
- Organization
- 0 DEDICATED INPUTS, 193 I/O
- Output Function
- MACROCELL
- Package Body Material
- PLASTIC/EPOXY
- Package Code
- BGA
- Package Shape
- SQUARE
- Package Style
- GRID ARRAY
- Peak Reflow Temperature (Cel)
- 250
- Programmable Logic Type
- EE PLD
- Propagation Delay
- 5.7 ns
- Qualification Status
- Not Qualified
- Seated Height-Max
- 2.1 mm
- Supply Voltage-Max
- 3.6 V
- Supply Voltage-Min
- 3 V
- Supply Voltage-Nom
- 3.3 V
- Surface Mount
- YES
- Technology
- CMOS
- Terminal Finish
- Tin/Silver/Copper (Sn/Ag/Cu)
- Terminal Form
- BALL
- Terminal Pitch
- 1 mm
- Terminal Position
- BOTTOM
- Time@Peak Reflow Temperature-Max (s)
- 40
- Width
- 17 mm
Download datasheets and manufacturer documentation for LATTICE LC5512MV-45FN256C.
Datasheets:
LC5512MV-45FN256C Overview
There are 512 macro cells, which are cells in a mobile phone network that provides radio coverage served by a high-power cell site (tower, antenna or mast).It is embedded in the 256-BGA package.It is programmed with 193 I/Os.There are 256 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.The terminal position of this electrical part is BOTTOM, which serves as an important access point for passengers or freight.It is powered from a supply voltage of 3.3V.This part is included in Programmable Logic Devices.It is packaged in the way of Tray.It operates with the operating temperature of 0°C~90°C TJ to ensure its reliability.It is mounted in the way of Surface Mount.It is a type of FPGA belonging to the ispXPLD® 5000MV series.It is equipped with 256 pin count.It is also characterized by YES.According to the LC5512, its related parts can be found.The supply voltage should be maintained at 3.3V for high efficiency.EEPROM, SRAM is adopted for storing data.This electronic part is mounted in the way of Surface Mount.It is designed with 256 pins.It operates with the maximal supply voltage of 3.6V.It operates with the minimal supply voltage of 3V.There are 16 logic elements/blocks, which are fundamental building blocks of field-programmable gate array (FPGA) technology.There are 176 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. The frequency that can be achieved is 333MHz.
LC5512MV-45FN256C Features
256-BGA package
193 I/Os
The operating temperature of 0°C~90°C TJ
256 pin count
256 pins
LC5512MV-45FN256C Applications
There are a lot of Lattice Semiconductor Corporation
LC5512MV-45FN256C CPLDs applications.
- Power up sequencing
- Voltage level translation
- Timing control
- Interface bridging
- I/O expansion
- Discrete logic functions
- Bootloaders for FPGAs
- Address decoders
- Custom state machines
- Digital systems
User Guide
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