LATTICE LC4256V-75FTN256AC

Manufacturer No:

LC4256V-75FTN256AC

Manufacturer:

LATTICE

Package:

FTBGA-256

Description:

EE PLD, 7.5ns, 256-Cell, CMOS, PBGA256, FTBGA-256

Quantity:

Delivery:

Payment:

In Stock :Available

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LC4256V-75FTN256AC information

LATTICE LC4256V-75FTN256AC technical specifications, attributes, parameters and parts with similar specifications to LATTICE LC4256V-75FTN256AC.

Type
Parameter

Pbfree Code
Yes

RoHS Status
RoHS Compliant

Part Life Cycle Code
Active

Ihs Manufacturer
LATTICE SEMICONDUCTOR CORP

Part Package Code
BGA

Package Description
FTBGA-256

Pin Count
256

Reach Compliance Code
compliant

ECCN Code
EAR99

HTS Code
8542.39.00.01

Samacsys Manufacturer
Lattice Semiconductor

Architecture
PAD-TYPE

Clock Frequency-Max
111 MHz

In-System Programmable
YES

JESD-30 Code
S-PBGA-B256

JESD-609 Code
e1

JTAG BST
YES

Length
17 mm

Moisture Sensitivity Level
3

Number of Dedicated Inputs
4

Number of I/O Lines
128

Number of Inputs
132

Number of Macro Cells
256

Number of Outputs
128

Number of Terminals
256

Operating Temperature-Max
90 °C

Organization
4 DEDICATED INPUTS, 128 I/O

Output Function
MACROCELL

Package Body Material
PLASTIC/EPOXY

Package Code
LBGA

Package Equivalence Code
BGA256,16X16,40

Package Shape
SQUARE

Package Style
GRID ARRAY, LOW PROFILE

Peak Reflow Temperature (Cel)
260

Programmable Logic Type
EE PLD

Propagation Delay
7.5 ns

Qualification Status
Not Qualified

Seated Height-Max
1.55 mm

Supply Voltage-Max
3.6 V

Supply Voltage-Min
3 V

Supply Voltage-Nom
3.3 V

Surface Mount
YES

Terminal Finish
Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

Terminal Form
BALL

Terminal Pitch
1 mm

Terminal Position
BOTTOM

Time@Peak Reflow Temperature-Max (s)
40

Download datasheets and manufacturer documentation for LATTICE LC4256V-75FTN256AC.

Datasheets:

LATT-S-A0013140030-1.pdf

LC4256V-75FTN256AC Overview

This network has 256macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).You can find it in package 256-LBGA.As a result, it has 128 I/O ports programmed.256 terminations have been programmed into the device.Its terminal position is BOTTOM.It is powered by a voltage of 3.3V volts.This part is part of the family Programmable Logic Devices.Package the chip by Tray.In order to ensure the reliability of the device, it is designed to operate at a temperature of [0].Chips should be mounted by Surface Mount.In terms of FPGAs, it belongs to the ispMACH® 4000V series.It has 256 pins programmed.This device can also display YES.Its related parts can be found in the [0].It is recommended that the supply voltage be kept at 3.3Vto maximize efficiency.It is adopted to store data in EEPROM.The electronic component is mounted by Surface Mount.In this case, the maximum supply voltage is 3.6V.Despite its minimal supply voltage of 3V, it is capable of operating.This logic block consists of 16 logic elements.There are 160 programmable I/Os in this system.In this case, 178.57MHz is the frequency that can be achieved.Input signals are detected by 4 dedicated inputs.A fundamental building block of logic consists of 540 logic elements/cells.

LC4256V-75FTN256AC Features

256-LBGA package
128 I/Os
The operating temperature of 0°C~90°C TJ
256 pin count

LC4256V-75FTN256AC Applications

There are a lot of Lattice Semiconductor Corporation
LC4256V-75FTN256AC CPLDs applications.

Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
Digital designs

User Guide

PURCHASE

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IMPORTANT NOTICE

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SHIPPING COST

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SHIPPING METHOD

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DELIVERY TIME

1. Once the goods are shipped, estimated delivery time depends on the shipping methods you chose: FedEx International, 5-7 business days.
2. For in-stock parts, orders normally could be shipped out within 1-2days.